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std.atomic: Implement specialized spinLoopHint() for more architectures.
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@ -378,21 +378,33 @@ pub inline fn spinLoopHint() void {
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// No-op instruction that can hint to save (or share with a hardware-thread)
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// pipelining/power resources
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// https://software.intel.com/content/www/us/en/develop/articles/benefitting-power-and-performance-sleep-loops.html
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.x86, .x86_64 => asm volatile ("pause" ::: "memory"),
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.x86,
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.x86_64,
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=> asm volatile ("pause" ::: "memory"),
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// No-op instruction that serves as a hardware-thread resource yield hint.
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// https://stackoverflow.com/a/7588941
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.powerpc64, .powerpc64le => asm volatile ("or 27, 27, 27" ::: "memory"),
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.powerpc,
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.powerpcle,
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.powerpc64,
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.powerpc64le,
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=> asm volatile ("or 27, 27, 27" ::: "memory"),
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// `isb` appears more reliable for releasing execution resources than `yield`
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// on common aarch64 CPUs.
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// https://bugs.java.com/bugdatabase/view_bug.do?bug_id=8258604
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// https://bugs.mysql.com/bug.php?id=100664
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.aarch64, .aarch64_be => asm volatile ("isb" ::: "memory"),
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.aarch64,
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.aarch64_be,
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=> asm volatile ("isb" ::: "memory"),
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// `yield` was introduced in v6k but is also available on v6m.
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// https://www.keil.com/support/man/docs/armasm/armasm_dom1361289926796.htm
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.arm, .armeb, .thumb, .thumbeb => {
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.arm,
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.armeb,
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.thumb,
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.thumbeb,
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=> {
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const can_yield = comptime std.Target.arm.featureSetHasAny(builtin.target.cpu.features, .{
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.has_v6k, .has_v6m,
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});
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@ -402,6 +414,22 @@ pub inline fn spinLoopHint() void {
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asm volatile ("" ::: "memory");
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}
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},
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// The 8-bit immediate specifies the amount of cycles to pause for. We can't really be too
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// opinionated here.
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.hexagon,
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=> asm volatile ("pause(#1)" ::: "memory"),
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.riscv32,
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.riscv64,
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=> {
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if (comptime std.Target.riscv.featureSetHas(builtin.target.cpu.features, .zihintpause)) {
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asm volatile ("pause" ::: "memory");
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} else {
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asm volatile ("" ::: "memory");
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}
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},
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// Memory barrier to prevent the compiler from optimizing away the spin-loop
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// even if no hint_instruction was provided.
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else => asm volatile ("" ::: "memory"),
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