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std.atomic: Define specialized cache_line values for more architectures.

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Alex Rønne Petersen 2024-07-27 11:44:11 +02:00
parent 390c7d84b2
commit 5b68595255
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1 changed files with 41 additions and 6 deletions
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lib/std/atomic.zig
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@ -429,26 +429,61 @@ pub const cache_line = switch (builtin.cpu.arch) {
// - https://www.mono-project.com/news/2016/09/12/arm64-icache/
// - https://cpufun.substack.com/p/more-m1-fun-hardware-information
//
// powerpc64: PPC has 128-byte cache lines
// - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/arc/Kconfig#L212
// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_ppc64x.go#L9
.x86_64, .aarch64, .powerpc64 => 128,
.x86_64,
.aarch64,
.aarch64_be,
.arc,
.powerpc64,
.powerpc64le,
=> 128,
// These platforms reportedly have 32-byte cache lines
// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_arm.go#L7
// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips.go#L7
// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mipsle.go#L7
// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips64x.go#L9
// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_riscv64.go#L7
.arm, .mips, .mips64, .riscv64 => 32,
// - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/hexagon/include/asm/cache.h#L13
// - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/sparc/include/asm/cache.h#L14
.arm,
.armeb,
.thumb,
.thumbeb,
.hexagon,
.mips,
.mipsel,
.mips64,
.mips64el,
.riscv32,
.riscv64,
.sparc,
.sparcel,
.sparc64,
=> 32,
// - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/m68k/include/asm/cache.h#L10
.m68k,
=> 16,
// - https://www.ti.com/lit/pdf/slaa498
.msp430,
=> 8,
// This platform reportedly has 256-byte cache lines
// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_s390x.go#L7
.s390x => 256,
// - https://sxauroratsubasa.sakura.ne.jp/documents/guide/pdfs/Aurora_ISA_guide.pdf
.s390x,
.ve,
=> 256,
// Other x86 and WASM platforms have 64-byte cache lines.
// The rest of the architectures are assumed to be similar.
// - https://github.com/golang/go/blob/dda2991c2ea0c5914714469c4defc2562a907230/src/internal/cpu/cpu_x86.go#L9
// - https://github.com/golang/go/blob/0a9321ad7f8c91e1b0c7184731257df923977eb9/src/internal/cpu/cpu_loong64.go#L11
// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_wasm.go#L7
// - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/xtensa/variants/csp/include/variant/core.h#L209
// - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/csky/Kconfig#L183
// - https://www.xmos.com/download/The-XMOS-XS3-Architecture.pdf
else => 64,
};