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stage2 ARM: move mul to binOp lowering mechanism
This commit is contained in:
joachimschmidt557
parent
67e3346633
commit
985a442f46
@ -508,7 +508,7 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void {
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.sub, .ptr_sub => try self.airBinOp(inst),
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.subwrap => try self.airSubWrap(inst),
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.sub_sat => try self.airSubSat(inst),
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.mul => try self.airMul(inst),
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.mul => try self.airBinOp(inst),
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.mulwrap => try self.airMulWrap(inst),
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.mul_sat => try self.airMulSat(inst),
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.rem => try self.airRem(inst),
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@ -979,12 +979,6 @@ fn airSubSat(self: *Self, inst: Air.Inst.Index) !void {
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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fn airMul(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else try self.genMul(inst, bin_op.lhs, bin_op.rhs);
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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fn airMulWrap(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else return self.fail("TODO implement mulwrap for {}", .{self.target.cpu.arch});
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@ -1252,7 +1246,7 @@ fn airSliceElemVal(self: *Self, inst: Air.Inst.Index) !void {
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const slice_ty = self.air.typeOf(bin_op.lhs);
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const elem_ty = slice_ty.childType();
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const elem_size = elem_ty.abiSize(self.target.*);
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const elem_size = @intCast(u32, elem_ty.abiSize(self.target.*));
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var buf: Type.SlicePtrFieldTypeBuffer = undefined;
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const slice_ptr_field_type = slice_ty.slicePtrFieldType(&buf);
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@ -1307,7 +1301,14 @@ fn airSliceElemVal(self: *Self, inst: Air.Inst.Index) !void {
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else => {
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const dst_mcv = try self.allocRegOrMem(inst, true);
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const offset_mcv = try self.genMulConstant(bin_op.rhs, @intCast(u32, elem_size));
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const offset_mcv = try self.binOp(
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.mul,
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null,
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index_mcv,
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.{ .immediate = elem_size },
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Type.usize,
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Type.usize,
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);
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assert(offset_mcv == .register); // result of multiplication should always be register
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self.register_manager.freezeRegs(&.{offset_mcv.register});
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@ -1768,6 +1769,7 @@ fn binOpRegister(
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const mir_tag: Mir.Inst.Tag = switch (tag) {
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.add, .ptr_add => .add,
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.sub, .ptr_sub => .sub,
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.mul => .mul,
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else => unreachable,
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};
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const mir_data: Mir.Inst.Data = switch (tag) {
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@ -1780,6 +1782,11 @@ fn binOpRegister(
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.rn = lhs_reg,
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.op = Instruction.Operand.reg(rhs_reg, Instruction.Operand.Shift.none),
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} },
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.mul => .{ .rrr = .{
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.rd = dest_reg,
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.rn = lhs_reg,
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.rm = rhs_reg,
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} },
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else => unreachable,
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};
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@ -1938,6 +1945,25 @@ fn binOp(
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else => unreachable,
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}
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},
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.mul => {
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switch (lhs_ty.zigTypeTag()) {
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.Float => return self.fail("TODO ARM binary operations on floats", .{}),
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.Vector => return self.fail("TODO ARM binary operations on vectors", .{}),
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.Int => {
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assert(lhs_ty.eql(rhs_ty));
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 32) {
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// TODO add optimisations for multiplication
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// with immediates, for example a * 2 can be
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// lowered to a << 1
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return try self.binOpRegister(tag, maybe_inst, lhs, rhs, lhs_ty, rhs_ty);
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} else {
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return self.fail("TODO ARM binary operations on integers > u32/i32", .{});
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}
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},
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else => unreachable,
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}
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},
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.ptr_add,
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.ptr_sub,
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=> {
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@ -2219,132 +2245,6 @@ fn genBinOpCode(
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}
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}
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fn genMul(self: *Self, inst: Air.Inst.Index, op_lhs: Air.Inst.Ref, op_rhs: Air.Inst.Ref) !MCValue {
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const lhs = try self.resolveInst(op_lhs);
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const rhs = try self.resolveInst(op_rhs);
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const lhs_is_register = lhs == .register;
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const rhs_is_register = rhs == .register;
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const reuse_lhs = lhs_is_register and self.reuseOperand(inst, op_lhs, 0, lhs);
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const reuse_rhs = !reuse_lhs and rhs_is_register and self.reuseOperand(inst, op_rhs, 1, rhs);
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if (lhs_is_register) self.register_manager.freezeRegs(&.{lhs.register});
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defer if (lhs_is_register) self.register_manager.unfreezeRegs(&.{lhs.register});
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if (rhs_is_register) self.register_manager.freezeRegs(&.{rhs.register});
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defer if (rhs_is_register) self.register_manager.unfreezeRegs(&.{rhs.register});
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// Destination must be a register
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// LHS must be a register
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// RHS must be a register
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var dst_mcv: MCValue = undefined;
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var lhs_mcv: MCValue = lhs;
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var rhs_mcv: MCValue = rhs;
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// Allocate registers for operands and/or destination
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const branch = &self.branch_stack.items[self.branch_stack.items.len - 1];
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if (reuse_lhs) {
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// Allocate 0 or 1 registers
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if (!rhs_is_register) {
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rhs_mcv = MCValue{ .register = try self.register_manager.allocReg(Air.refToIndex(op_rhs).?) };
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branch.inst_table.putAssumeCapacity(Air.refToIndex(op_rhs).?, rhs_mcv);
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}
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dst_mcv = lhs;
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} else if (reuse_rhs) {
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// Allocate 0 or 1 registers
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if (!lhs_is_register) {
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lhs_mcv = MCValue{ .register = try self.register_manager.allocReg(Air.refToIndex(op_lhs).?) };
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branch.inst_table.putAssumeCapacity(Air.refToIndex(op_lhs).?, lhs_mcv);
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}
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dst_mcv = rhs;
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} else {
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// Allocate 1 or 2 registers
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if (lhs_is_register and rhs_is_register) {
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dst_mcv = MCValue{ .register = try self.register_manager.allocReg(inst) };
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} else if (lhs_is_register) {
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// Move RHS to register
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dst_mcv = MCValue{ .register = try self.register_manager.allocReg(inst) };
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rhs_mcv = dst_mcv;
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} else if (rhs_is_register) {
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// Move LHS to register
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dst_mcv = MCValue{ .register = try self.register_manager.allocReg(inst) };
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lhs_mcv = dst_mcv;
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} else {
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// Move LHS and RHS to register
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const regs = try self.register_manager.allocRegs(2, .{ inst, Air.refToIndex(op_rhs).? });
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lhs_mcv = MCValue{ .register = regs[0] };
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rhs_mcv = MCValue{ .register = regs[1] };
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dst_mcv = lhs_mcv;
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branch.inst_table.putAssumeCapacity(Air.refToIndex(op_rhs).?, rhs_mcv);
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}
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}
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// Move the operands to the newly allocated registers
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if (!lhs_is_register) {
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try self.genSetReg(self.air.typeOf(op_lhs), lhs_mcv.register, lhs);
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}
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if (!rhs_is_register) {
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try self.genSetReg(self.air.typeOf(op_rhs), rhs_mcv.register, rhs);
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}
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_ = try self.addInst(.{
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.tag = .mul,
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.data = .{ .rrr = .{
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.rd = dst_mcv.register,
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.rn = lhs_mcv.register,
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.rm = rhs_mcv.register,
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} },
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});
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return dst_mcv;
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}
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fn genMulConstant(self: *Self, op: Air.Inst.Ref, imm: u32) !MCValue {
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const lhs = try self.resolveInst(op);
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const rhs = MCValue{ .immediate = imm };
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const lhs_is_register = lhs == .register;
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if (lhs_is_register) self.register_manager.freezeRegs(&.{lhs.register});
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defer if (lhs_is_register) self.register_manager.unfreezeRegs(&.{lhs.register});
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// Destination must be a register
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// LHS must be a register
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// RHS must be a register
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var dst_mcv: MCValue = undefined;
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var lhs_mcv: MCValue = lhs;
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var rhs_mcv: MCValue = rhs;
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// Allocate registers for operands and/or destination
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// Allocate 1 or 2 registers
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if (lhs_is_register) {
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// Move RHS to register
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dst_mcv = MCValue{ .register = try self.register_manager.allocReg(null) };
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rhs_mcv = dst_mcv;
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} else {
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// Move LHS and RHS to register
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const regs = try self.register_manager.allocRegs(2, .{ null, null });
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lhs_mcv = MCValue{ .register = regs[0] };
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rhs_mcv = MCValue{ .register = regs[1] };
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dst_mcv = lhs_mcv;
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}
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// Move the operands to the newly allocated registers
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if (!lhs_is_register) {
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try self.genSetReg(self.air.typeOf(op), lhs_mcv.register, lhs);
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}
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try self.genSetReg(Type.initTag(.usize), rhs_mcv.register, rhs);
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_ = try self.addInst(.{
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.tag = .mul,
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.data = .{ .rrr = .{
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.rd = dst_mcv.register,
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.rn = lhs_mcv.register,
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.rm = rhs_mcv.register,
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} },
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});
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return dst_mcv;
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}
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fn genLdrRegister(self: *Self, dest_reg: Register, addr_reg: Register, abi_size: u32) !void {
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switch (abi_size) {
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1, 3, 4 => {
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