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https://github.com/ziglang/zig.git
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stage2 ARM: move add and sub to new binOp lowering mechanism
This commit is contained in:
joachimschmidt557
parent
23915c2c44
commit
67e3346633
@ -502,10 +502,10 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void {
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switch (air_tags[inst]) {
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// zig fmt: off
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.add, .ptr_add => try self.airAdd(inst),
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.add, .ptr_add => try self.airBinOp(inst),
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.addwrap => try self.airAddWrap(inst),
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.add_sat => try self.airAddSat(inst),
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.sub, .ptr_sub => try self.airSub(inst),
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.sub, .ptr_sub => try self.airBinOp(inst),
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.subwrap => try self.airSubWrap(inst),
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.sub_sat => try self.airSubSat(inst),
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.mul => try self.airMul(inst),
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@ -943,9 +943,15 @@ fn airSlice(self: *Self, inst: Air.Inst.Index) !void {
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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fn airAdd(self: *Self, inst: Air.Inst.Index) !void {
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fn airBinOp(self: *Self, inst: Air.Inst.Index) !void {
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const tag = self.air.instructions.items(.tag)[inst];
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else try self.genBinOp(inst, bin_op.lhs, bin_op.rhs, .add);
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const lhs = try self.resolveInst(bin_op.lhs);
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const rhs = try self.resolveInst(bin_op.rhs);
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const lhs_ty = self.air.typeOf(bin_op.lhs);
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const rhs_ty = self.air.typeOf(bin_op.rhs);
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else try self.binOp(tag, inst, lhs, rhs, lhs_ty, rhs_ty);
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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@ -961,12 +967,6 @@ fn airAddSat(self: *Self, inst: Air.Inst.Index) !void {
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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fn airSub(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else try self.genBinOp(inst, bin_op.lhs, bin_op.rhs, .sub);
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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fn airSubWrap(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else return self.fail("TODO implement subwrap for {}", .{self.target.cpu.arch});
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@ -1311,18 +1311,14 @@ fn airSliceElemVal(self: *Self, inst: Air.Inst.Index) !void {
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assert(offset_mcv == .register); // result of multiplication should always be register
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self.register_manager.freezeRegs(&.{offset_mcv.register});
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const addr_reg = try self.register_manager.allocReg(null);
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self.register_manager.freezeRegs(&.{addr_reg});
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defer self.register_manager.unfreezeRegs(&.{addr_reg});
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try self.genBinOpCode(addr_reg, base_mcv, offset_mcv, false, .add, .unsigned);
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const addr_mcv = try self.binOp(.add, null, base_mcv, offset_mcv, Type.usize, Type.usize);
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// At this point in time, neither the base register
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// nor the offset register contains any valuable data
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// anymore.
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self.register_manager.unfreezeRegs(&.{ base_mcv.register, offset_mcv.register });
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try self.load(dst_mcv, .{ .register = addr_reg }, slice_ptr_field_type);
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try self.load(dst_mcv, addr_mcv, slice_ptr_field_type);
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break :result dst_mcv;
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},
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@ -1652,16 +1648,16 @@ fn structFieldPtr(self: *Self, inst: Air.Inst.Index, operand: Air.Inst.Ref, inde
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self.register_manager.freezeRegs(&.{addr_reg});
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defer self.register_manager.unfreezeRegs(&.{addr_reg});
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const dst_reg = try self.register_manager.allocReg(inst);
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try self.genBinOpCode(
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dst_reg,
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const dest = try self.binOp(
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.add,
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null,
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.{ .register = addr_reg },
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.{ .register = offset_reg },
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false,
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.add,
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.unsigned,
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Type.usize,
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Type.usize,
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);
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break :result MCValue{ .register = dst_reg };
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break :result dest;
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},
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}
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};
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@ -1699,6 +1695,273 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void {
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return self.finishAir(inst, result, .{ extra.struct_operand, .none, .none });
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}
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/// Don't call this function directly. Use binOp instead.
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///
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/// Calling this function signals an intention to generate a Mir
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/// instruction of the form
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///
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/// op dest, lhs, rhs
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///
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/// Asserts that generating an instruction of that form is possible.
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fn binOpRegister(
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self: *Self,
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tag: Air.Inst.Tag,
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maybe_inst: ?Air.Inst.Index,
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lhs: MCValue,
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rhs: MCValue,
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lhs_ty: Type,
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rhs_ty: Type,
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) !MCValue {
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const lhs_is_register = lhs == .register;
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const rhs_is_register = rhs == .register;
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if (lhs_is_register) self.register_manager.freezeRegs(&.{lhs.register});
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if (rhs_is_register) self.register_manager.freezeRegs(&.{rhs.register});
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const branch = &self.branch_stack.items[self.branch_stack.items.len - 1];
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const lhs_reg = if (lhs_is_register) lhs.register else blk: {
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const track_inst: ?Air.Inst.Index = if (maybe_inst) |inst| inst: {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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break :inst Air.refToIndex(bin_op.lhs).?;
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} else null;
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const reg = try self.register_manager.allocReg(track_inst);
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self.register_manager.freezeRegs(&.{reg});
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if (track_inst) |inst| branch.inst_table.putAssumeCapacity(inst, .{ .register = reg });
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break :blk reg;
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};
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defer self.register_manager.unfreezeRegs(&.{lhs_reg});
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const rhs_reg = if (rhs_is_register) rhs.register else blk: {
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const track_inst: ?Air.Inst.Index = if (maybe_inst) |inst| inst: {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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break :inst Air.refToIndex(bin_op.rhs).?;
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} else null;
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const reg = try self.register_manager.allocReg(track_inst);
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self.register_manager.freezeRegs(&.{reg});
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if (track_inst) |inst| branch.inst_table.putAssumeCapacity(inst, .{ .register = reg });
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break :blk reg;
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};
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defer self.register_manager.unfreezeRegs(&.{rhs_reg});
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const dest_reg = if (maybe_inst) |inst| blk: {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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if (lhs_is_register and self.reuseOperand(inst, bin_op.lhs, 0, lhs)) {
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break :blk lhs_reg;
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} else if (rhs_is_register and self.reuseOperand(inst, bin_op.rhs, 1, rhs)) {
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break :blk rhs_reg;
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} else {
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break :blk try self.register_manager.allocReg(inst);
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}
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} else try self.register_manager.allocReg(null);
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if (!lhs_is_register) try self.genSetReg(lhs_ty, lhs_reg, lhs);
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if (!rhs_is_register) try self.genSetReg(rhs_ty, rhs_reg, rhs);
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const mir_tag: Mir.Inst.Tag = switch (tag) {
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.add, .ptr_add => .add,
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.sub, .ptr_sub => .sub,
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else => unreachable,
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};
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const mir_data: Mir.Inst.Data = switch (tag) {
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.add,
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.sub,
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.ptr_add,
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.ptr_sub,
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=> .{ .rr_op = .{
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.rd = dest_reg,
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.rn = lhs_reg,
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.op = Instruction.Operand.reg(rhs_reg, Instruction.Operand.Shift.none),
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} },
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else => unreachable,
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};
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_ = try self.addInst(.{
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.tag = mir_tag,
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.data = mir_data,
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});
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return MCValue{ .register = dest_reg };
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}
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/// Don't call this function directly. Use binOp instead.
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///
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/// Calling this function signals an intention to generate a Mir
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/// instruction of the form
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///
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/// op dest, lhs, #rhs_imm
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///
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/// Set lhs_and_rhs_swapped to true iff inst.bin_op.lhs corresponds to
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/// rhs and vice versa. This parameter is only used when maybe_inst !=
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/// null.
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///
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/// Asserts that generating an instruction of that form is possible.
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fn binOpImmediate(
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self: *Self,
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tag: Air.Inst.Tag,
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maybe_inst: ?Air.Inst.Index,
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lhs: MCValue,
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rhs: MCValue,
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lhs_ty: Type,
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lhs_and_rhs_swapped: bool,
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) !MCValue {
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const lhs_is_register = lhs == .register;
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if (lhs_is_register) self.register_manager.freezeRegs(&.{lhs.register});
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const branch = &self.branch_stack.items[self.branch_stack.items.len - 1];
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const lhs_reg = if (lhs_is_register) lhs.register else blk: {
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const track_inst: ?Air.Inst.Index = if (maybe_inst) |inst| inst: {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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break :inst Air.refToIndex(
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if (lhs_and_rhs_swapped) bin_op.rhs else bin_op.lhs,
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).?;
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} else null;
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const reg = try self.register_manager.allocReg(track_inst);
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self.register_manager.freezeRegs(&.{reg});
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if (track_inst) |inst| branch.inst_table.putAssumeCapacity(inst, .{ .register = reg });
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break :blk reg;
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};
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defer self.register_manager.unfreezeRegs(&.{lhs_reg});
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const dest_reg = if (maybe_inst) |inst| blk: {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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if (lhs_is_register and self.reuseOperand(
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inst,
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if (lhs_and_rhs_swapped) bin_op.rhs else bin_op.lhs,
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if (lhs_and_rhs_swapped) 1 else 0,
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lhs,
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)) {
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break :blk lhs_reg;
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} else {
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break :blk try self.register_manager.allocReg(inst);
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}
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} else try self.register_manager.allocReg(null);
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if (!lhs_is_register) try self.genSetReg(lhs_ty, lhs_reg, lhs);
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const mir_tag: Mir.Inst.Tag = switch (tag) {
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.add => .add,
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.sub => .sub,
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else => unreachable,
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};
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const mir_data: Mir.Inst.Data = switch (tag) {
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.add,
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.sub,
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=> .{ .rr_op = .{
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.rd = dest_reg,
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.rn = lhs_reg,
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.op = Instruction.Operand.fromU32(rhs.immediate).?,
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} },
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else => unreachable,
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};
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_ = try self.addInst(.{
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.tag = mir_tag,
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.data = mir_data,
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});
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return MCValue{ .register = dest_reg };
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}
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/// For all your binary operation needs, this function will generate
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/// the corresponding Mir instruction(s). Returns the location of the
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/// result.
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///
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/// If the binary operation itself happens to be an Air instruction,
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/// pass the corresponding index in the inst parameter. That helps
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/// this function do stuff like reusing operands.
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///
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/// This function does not do any lowering to Mir itself, but instead
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/// looks at the lhs and rhs and determines which kind of lowering
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/// would be best suitable and then delegates the lowering to other
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/// functions.
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fn binOp(
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self: *Self,
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tag: Air.Inst.Tag,
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maybe_inst: ?Air.Inst.Index,
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lhs: MCValue,
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rhs: MCValue,
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lhs_ty: Type,
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rhs_ty: Type,
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) !MCValue {
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switch (tag) {
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.add,
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.sub,
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=> {
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switch (lhs_ty.zigTypeTag()) {
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.Float => return self.fail("TODO ARM binary operations on floats", .{}),
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.Vector => return self.fail("TODO ARM binary operations on vectors", .{}),
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.Int => {
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assert(lhs_ty.eql(rhs_ty));
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 32) {
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// Only say yes if the operation is
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// commutative, i.e. we can swap both of the
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// operands
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const lhs_immediate_ok = switch (tag) {
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.add => lhs == .immediate and Instruction.Operand.fromU32(lhs.immediate) != null,
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.sub => false,
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else => unreachable,
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};
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const rhs_immediate_ok = switch (tag) {
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.add,
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.sub,
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=> rhs == .immediate and Instruction.Operand.fromU32(rhs.immediate) != null,
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else => unreachable,
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};
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if (rhs_immediate_ok) {
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return try self.binOpImmediate(tag, maybe_inst, lhs, rhs, lhs_ty, false);
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} else if (lhs_immediate_ok) {
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// swap lhs and rhs
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return try self.binOpImmediate(tag, maybe_inst, rhs, lhs, rhs_ty, true);
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} else {
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return try self.binOpRegister(tag, maybe_inst, lhs, rhs, lhs_ty, rhs_ty);
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}
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} else {
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return self.fail("TODO ARM binary operations on integers > u32/i32", .{});
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}
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},
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else => unreachable,
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}
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},
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.ptr_add,
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.ptr_sub,
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=> {
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switch (lhs_ty.zigTypeTag()) {
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.Pointer => {
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const ptr_ty = lhs_ty;
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const pointee_ty = switch (ptr_ty.ptrSize()) {
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.One => ptr_ty.childType().childType(), // ptr to array, so get array element type
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else => ptr_ty.childType(),
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};
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if (pointee_ty.abiSize(self.target.*) > 1) {
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return self.fail("TODO ptr_add, ptr_sub with more element sizes", .{});
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}
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return try self.binOpRegister(tag, maybe_inst, lhs, rhs, lhs_ty, rhs_ty);
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},
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else => unreachable,
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}
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},
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else => unreachable,
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}
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}
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fn armOperandShouldBeRegister(self: *Self, mcv: MCValue) !bool {
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return switch (mcv) {
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.none => unreachable,
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@ -1730,8 +1993,6 @@ fn genBinOp(self: *Self, inst: Air.Inst.Index, op_lhs: Air.Inst.Ref, op_rhs: Air
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const ty = self.air.typeOf(op_lhs);
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switch (ty.zigTypeTag()) {
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.Float => return self.fail("TODO ARM binary operations on floats", .{}),
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.Vector => return self.fail("TODO ARM binary operations on vectors", .{}),
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.Bool => {
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return self.genBinIntOp(inst, op_lhs, op_rhs, op, 1, .unsigned);
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},
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@ -1896,7 +2157,6 @@ fn genBinOpCode(
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};
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switch (op) {
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.add,
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.bool_and,
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.bit_and,
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.bool_or,
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@ -1905,7 +2165,6 @@ fn genBinOpCode(
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.xor,
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=> {
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const tag: Mir.Inst.Tag = switch (op) {
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.add => .add,
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.bool_and, .bit_and => .@"and",
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.bool_or, .bit_or => .orr,
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.not, .xor => .eor,
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@ -1921,18 +2180,6 @@ fn genBinOpCode(
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} },
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});
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},
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.sub => {
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const tag: Mir.Inst.Tag = if (swap_lhs_and_rhs) .rsb else .sub;
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_ = try self.addInst(.{
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.tag = tag,
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.data = .{ .rr_op = .{
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.rd = dst_reg,
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.rn = op1,
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.op = operand,
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} },
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});
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},
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.cmp_eq => {
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_ = try self.addInst(.{
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.tag = .cmp,
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