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std.Target: Update CPU models/features for LLVM 19.1.0.

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Alex Rønne Petersen 2024-09-18 06:36:47 +02:00 committed by Andrew Kelley
parent a463c369cd
commit 916eaad1ef
3 changed files with 90 additions and 1 deletions
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2
lib/std/Target/aarch64.zig
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@ -2045,7 +2045,7 @@ pub const cpu = struct {
.sme2, .sme2,
.sme_f64f64, .sme_f64f64,
.sme_i16i64, .sme_i16i64,
.v9_2a, .v8_7a,
.zcm, .zcm,
.zcz, .zcz,
}), }),

12
lib/std/Target/amdgpu.zig
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@ -180,6 +180,7 @@ pub const Feature = enum {
vgpr_index_mode, vgpr_index_mode,
vgpr_singleuse_hint, vgpr_singleuse_hint,
vmem_to_scalar_write_hazard, vmem_to_scalar_write_hazard,
vmem_write_vgpr_in_order,
volcanic_islands, volcanic_islands,
vop3_literal, vop3_literal,
vop3p, vop3p,
@ -605,6 +606,7 @@ pub const all_features = blk: {
.sdwa_sdst, .sdwa_sdst,
.unaligned_buffer_access, .unaligned_buffer_access,
.unaligned_ds_access, .unaligned_ds_access,
.vmem_write_vgpr_in_order,
.vop3_literal, .vop3_literal,
.vop3p, .vop3p,
.vscnt, .vscnt,
@ -675,6 +677,7 @@ pub const all_features = blk: {
.true16, .true16,
.unaligned_buffer_access, .unaligned_buffer_access,
.unaligned_ds_access, .unaligned_ds_access,
.vmem_write_vgpr_in_order,
.vop3_literal, .vop3_literal,
.vop3p, .vop3p,
.vopd, .vopd,
@ -791,6 +794,7 @@ pub const all_features = blk: {
.unaligned_buffer_access, .unaligned_buffer_access,
.unaligned_ds_access, .unaligned_ds_access,
.vgpr_index_mode, .vgpr_index_mode,
.vmem_write_vgpr_in_order,
.vop3p, .vop3p,
.wavefrontsize64, .wavefrontsize64,
.xnack_support, .xnack_support,
@ -1161,6 +1165,7 @@ pub const all_features = blk: {
.s_memtime_inst, .s_memtime_inst,
.trig_reduced_range, .trig_reduced_range,
.unaligned_buffer_access, .unaligned_buffer_access,
.vmem_write_vgpr_in_order,
.wavefrontsize64, .wavefrontsize64,
}), }),
}; };
@ -1209,6 +1214,7 @@ pub const all_features = blk: {
.movrel, .movrel,
.s_memtime_inst, .s_memtime_inst,
.trig_reduced_range, .trig_reduced_range,
.vmem_write_vgpr_in_order,
.wavefrontsize64, .wavefrontsize64,
}), }),
}; };
@ -1307,6 +1313,11 @@ pub const all_features = blk: {
.description = "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution.", .description = "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution.",
.dependencies = featureSet(&[_]Feature{}), .dependencies = featureSet(&[_]Feature{}),
}; };
result[@intFromEnum(Feature.vmem_write_vgpr_in_order)] = .{
.llvm_name = "vmem-write-vgpr-in-order",
.description = "VMEM instructions of the same type write VGPR results in order",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.volcanic_islands)] = .{ result[@intFromEnum(Feature.volcanic_islands)] = .{
.llvm_name = "volcanic-islands", .llvm_name = "volcanic-islands",
.description = "VOLCANIC_ISLANDS GPU generation", .description = "VOLCANIC_ISLANDS GPU generation",
@ -1341,6 +1352,7 @@ pub const all_features = blk: {
.trig_reduced_range, .trig_reduced_range,
.unaligned_buffer_access, .unaligned_buffer_access,
.vgpr_index_mode, .vgpr_index_mode,
.vmem_write_vgpr_in_order,
.wavefrontsize64, .wavefrontsize64,
}), }),
}; };

77
lib/std/Target/x86.zig
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@ -4819,4 +4819,81 @@ pub const cpu = struct {
.xsaves, .xsaves,
}), }),
}; };
pub const znver5 = CpuModel{
.name = "znver5",
.llvm_name = "znver5",
.features = featureSet(&[_]Feature{
.@"64bit",
.adx,
.allow_light_256_bit,
.avx512bf16,
.avx512bitalg,
.avx512cd,
.avx512dq,
.avx512ifma,
.avx512vbmi,
.avx512vbmi2,
.avx512vl,
.avx512vnni,
.avx512vp2intersect,
.avx512vpopcntdq,
.avxvnni,
.bmi,
.bmi2,
.branchfusion,
.clflushopt,
.clwb,
.clzero,
.cmov,
.crc32,
.cx16,
.evex512,
.fast_15bytenop,
.fast_bextr,
.fast_dpwssd,
.fast_imm16,
.fast_lzcnt,
.fast_movbe,
.fast_scalar_fsqrt,
.fast_scalar_shift_masks,
.fast_variable_perlane_shuffle,
.fast_vector_fsqrt,
.fsgsbase,
.fsrm,
.fxsr,
.gfni,
.idivq_to_divl,
.invpcid,
.lzcnt,
.macrofusion,
.mmx,
.movbe,
.movdir64b,
.movdiri,
.mwaitx,
.nopl,
.pku,
.popcnt,
.prefetchi,
.prfchw,
.rdpid,
.rdpru,
.rdrnd,
.rdseed,
.sahf,
.sbb_dep_breaking,
.sha,
.shstk,
.slow_shld,
.sse4a,
.vaes,
.vpclmulqdq,
.vzeroupper,
.wbnoinvd,
.x87,
.xsavec,
.xsaveopt,
.xsaves,
}),
};
}; };