diff --git a/lib/std/Target/aarch64.zig b/lib/std/Target/aarch64.zig
index 800918cc14..ac7dba124e 100644
--- a/lib/std/Target/aarch64.zig
+++ b/lib/std/Target/aarch64.zig
@@ -2045,7 +2045,7 @@ pub const cpu = struct {
             .sme2,
             .sme_f64f64,
             .sme_i16i64,
-            .v9_2a,
+            .v8_7a,
             .zcm,
             .zcz,
         }),
diff --git a/lib/std/Target/amdgpu.zig b/lib/std/Target/amdgpu.zig
index b6b03a6bce..a12e1b0c0b 100644
--- a/lib/std/Target/amdgpu.zig
+++ b/lib/std/Target/amdgpu.zig
@@ -180,6 +180,7 @@ pub const Feature = enum {
     vgpr_index_mode,
     vgpr_singleuse_hint,
     vmem_to_scalar_write_hazard,
+    vmem_write_vgpr_in_order,
     volcanic_islands,
     vop3_literal,
     vop3p,
@@ -605,6 +606,7 @@ pub const all_features = blk: {
             .sdwa_sdst,
             .unaligned_buffer_access,
             .unaligned_ds_access,
+            .vmem_write_vgpr_in_order,
             .vop3_literal,
             .vop3p,
             .vscnt,
@@ -675,6 +677,7 @@ pub const all_features = blk: {
             .true16,
             .unaligned_buffer_access,
             .unaligned_ds_access,
+            .vmem_write_vgpr_in_order,
             .vop3_literal,
             .vop3p,
             .vopd,
@@ -791,6 +794,7 @@ pub const all_features = blk: {
             .unaligned_buffer_access,
             .unaligned_ds_access,
             .vgpr_index_mode,
+            .vmem_write_vgpr_in_order,
             .vop3p,
             .wavefrontsize64,
             .xnack_support,
@@ -1161,6 +1165,7 @@ pub const all_features = blk: {
             .s_memtime_inst,
             .trig_reduced_range,
             .unaligned_buffer_access,
+            .vmem_write_vgpr_in_order,
             .wavefrontsize64,
         }),
     };
@@ -1209,6 +1214,7 @@ pub const all_features = blk: {
             .movrel,
             .s_memtime_inst,
             .trig_reduced_range,
+            .vmem_write_vgpr_in_order,
             .wavefrontsize64,
         }),
     };
@@ -1307,6 +1313,11 @@ pub const all_features = blk: {
         .description = "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution.",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@intFromEnum(Feature.vmem_write_vgpr_in_order)] = .{
+        .llvm_name = "vmem-write-vgpr-in-order",
+        .description = "VMEM instructions of the same type write VGPR results in order",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@intFromEnum(Feature.volcanic_islands)] = .{
         .llvm_name = "volcanic-islands",
         .description = "VOLCANIC_ISLANDS GPU generation",
@@ -1341,6 +1352,7 @@ pub const all_features = blk: {
             .trig_reduced_range,
             .unaligned_buffer_access,
             .vgpr_index_mode,
+            .vmem_write_vgpr_in_order,
             .wavefrontsize64,
         }),
     };
diff --git a/lib/std/Target/x86.zig b/lib/std/Target/x86.zig
index 5974fbc7d0..97ba84c00a 100644
--- a/lib/std/Target/x86.zig
+++ b/lib/std/Target/x86.zig
@@ -4819,4 +4819,81 @@ pub const cpu = struct {
             .xsaves,
         }),
     };
+    pub const znver5 = CpuModel{
+        .name = "znver5",
+        .llvm_name = "znver5",
+        .features = featureSet(&[_]Feature{
+            .@"64bit",
+            .adx,
+            .allow_light_256_bit,
+            .avx512bf16,
+            .avx512bitalg,
+            .avx512cd,
+            .avx512dq,
+            .avx512ifma,
+            .avx512vbmi,
+            .avx512vbmi2,
+            .avx512vl,
+            .avx512vnni,
+            .avx512vp2intersect,
+            .avx512vpopcntdq,
+            .avxvnni,
+            .bmi,
+            .bmi2,
+            .branchfusion,
+            .clflushopt,
+            .clwb,
+            .clzero,
+            .cmov,
+            .crc32,
+            .cx16,
+            .evex512,
+            .fast_15bytenop,
+            .fast_bextr,
+            .fast_dpwssd,
+            .fast_imm16,
+            .fast_lzcnt,
+            .fast_movbe,
+            .fast_scalar_fsqrt,
+            .fast_scalar_shift_masks,
+            .fast_variable_perlane_shuffle,
+            .fast_vector_fsqrt,
+            .fsgsbase,
+            .fsrm,
+            .fxsr,
+            .gfni,
+            .idivq_to_divl,
+            .invpcid,
+            .lzcnt,
+            .macrofusion,
+            .mmx,
+            .movbe,
+            .movdir64b,
+            .movdiri,
+            .mwaitx,
+            .nopl,
+            .pku,
+            .popcnt,
+            .prefetchi,
+            .prfchw,
+            .rdpid,
+            .rdpru,
+            .rdrnd,
+            .rdseed,
+            .sahf,
+            .sbb_dep_breaking,
+            .sha,
+            .shstk,
+            .slow_shld,
+            .sse4a,
+            .vaes,
+            .vpclmulqdq,
+            .vzeroupper,
+            .wbnoinvd,
+            .x87,
+            .xsavec,
+            .xsaveopt,
+            .xsaves,
+        }),
+    };
 };