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update the CPU target features and models

Browse Source 
Rather than directly pasting the output from the
target-details-generator tool, we have to look at the diff line by line
and decide how to incorporate the changes.

The baseline abstraction is something that Zig provides.

The changes to x86 appear to be incorrect. After LLVM commit
3ad09fd03c51823aeb0bcbd7898aada33e9228d6 the CPU features are stored in
a different data layout in their tables, and so we need to update the
target details extraction tool to match.
This commit is contained in:
Andrew Kelley 2020-12-16 17:25:48 -07:00
parent bbb3403b5d
commit 8f1408578c
17 changed files with 1029 additions and 1344 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
lib/std/target.zig
View File

@ -551,7 +551,7 @@ pub const Target = struct {
pub const Set = struct {
ints: [usize_count]usize,
pub const needed_bit_count = 192;
pub const needed_bit_count = 172;
pub const byte_count = (needed_bit_count + 7) / 8;
pub const usize_count = (byte_count + (@sizeOf(usize) - 1)) / @sizeOf(usize);
pub const Index = std.math.Log2Int(std.meta.Int(.unsigned, usize_count * @bitSizeOf(usize)));
@ -1149,9 +1149,9 @@ pub const Target = struct {
pub fn baseline(arch: Arch) *const Model {
return switch (arch) {
// .arm, .armeb, .thumb, .thumbeb => &arm.cpu.baseline, // TODO removed in LLVM 12
// .riscv32 => &riscv.cpu.baseline_rv32, // TODO removed in LLVM 12
// .riscv64 => &riscv.cpu.baseline_rv64, // TODO removed in LLVM 12
.arm, .armeb, .thumb, .thumbeb => &arm.cpu.baseline,
.riscv32 => &riscv.cpu.baseline_rv32,
.riscv64 => &riscv.cpu.baseline_rv64,
.i386 => &x86.cpu.pentium4,
.nvptx, .nvptx64 => &nvptx.cpu.sm_20,

732
lib/std/target/aarch64.zig
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File diff suppressed because it is too large Load Diff

11
lib/std/target/amdgpu.zig
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@ -9,7 +9,6 @@ const CpuModel = std.Target.Cpu.Model;
pub const Feature = enum {
@"16_bit_insts",
DumpCode,
a16,
add_no_carry_insts,
aperture_regs,
@ -27,7 +26,7 @@ pub const Feature = enum {
dpp,
dpp8,
ds_src2_insts,
dumpcode,
dump_code,
enable_ds128,
enable_prt_strict_null,
fast_denormal_f32,
@ -128,7 +127,6 @@ pub const Feature = enum {
pub usingnamespace CpuFeature.feature_set_fns(Feature);
pub const all_features = blk: {
@setEvalBranchQuota(10000);
const len = @typeInfo(Feature).Enum.fields.len;
std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
var result: [len]CpuFeature = undefined;
@ -137,11 +135,6 @@ pub const all_features = blk: {
.description = "Has i16/f16 instructions",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.DumpCode)] = .{
.llvm_name = "DumpCode",
.description = "Dump MachineInstrs in the CodeEmitter",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.a16)] = .{
.llvm_name = "a16",
.description = "Support gfx10-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands",
@ -229,7 +222,7 @@ pub const all_features = blk: {
.description = "Has ds_*_src2 instructions",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.dumpcode)] = .{
result[@enumToInt(Feature.dump_code)] = .{
.llvm_name = "dumpcode",
.description = "Dump MachineInstrs in the CodeEmitter",
.dependencies = featureSet(&[_]Feature{}),

1464
lib/std/target/arm.zig
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File diff suppressed because it is too large Load Diff

4
lib/std/target/avr.zig
View File

@ -47,7 +47,6 @@ pub const Feature = enum {
pub usingnamespace CpuFeature.feature_set_fns(Feature);
pub const all_features = blk: {
@setEvalBranchQuota(10000);
const len = @typeInfo(Feature).Enum.fields.len;
std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
var result: [len]CpuFeature = undefined;
@ -164,6 +163,7 @@ pub const all_features = blk: {
.dependencies = featureSet(&[_]Feature{
.avr0,
.@"break",
.memmappedregs,
.sram,
.tinyencoding,
}),
@ -1859,7 +1859,7 @@ pub const cpu = struct {
.name = "atxmega16e5",
.llvm_name = "atxmega16e5",
.features = featureSet(&[_]Feature{
.xmegau,
.xmega,
}),
};
pub const atxmega192a3 = CpuModel{

1
lib/std/target/bpf.zig
View File

@ -16,7 +16,6 @@ pub const Feature = enum {
pub usingnamespace CpuFeature.feature_set_fns(Feature);
pub const all_features = blk: {
@setEvalBranchQuota(10000);
const len = @typeInfo(Feature).Enum.fields.len;
std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
var result: [len]CpuFeature = undefined;

1
lib/std/target/hexagon.zig
View File

@ -44,7 +44,6 @@ pub const Feature = enum {
pub usingnamespace CpuFeature.feature_set_fns(Feature);
pub const all_features = blk: {
@setEvalBranchQuota(10000);
const len = @typeInfo(Feature).Enum.fields.len;
std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
var result: [len]CpuFeature = undefined;

1
lib/std/target/mips.zig
View File

@ -65,7 +65,6 @@ pub const Feature = enum {
pub usingnamespace CpuFeature.feature_set_fns(Feature);
pub const all_features = blk: {
@setEvalBranchQuota(10000);
const len = @typeInfo(Feature).Enum.fields.len;
std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
var result: [len]CpuFeature = undefined;

1
lib/std/target/msp430.zig
View File

@ -17,7 +17,6 @@ pub const Feature = enum {
pub usingnamespace CpuFeature.feature_set_fns(Feature);
pub const all_features = blk: {
@setEvalBranchQuota(10000);
const len = @typeInfo(Feature).Enum.fields.len;
std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
var result: [len]CpuFeature = undefined;

1
lib/std/target/nvptx.zig
View File

@ -41,7 +41,6 @@ pub const Feature = enum {
pub usingnamespace CpuFeature.feature_set_fns(Feature);
pub const all_features = blk: {
@setEvalBranchQuota(10000);
const len = @typeInfo(Feature).Enum.fields.len;
std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
var result: [len]CpuFeature = undefined;

91
lib/std/target/powerpc.zig
View File

@ -62,6 +62,7 @@ pub const Feature = enum {
ppc6xx,
predictable_select_expensive,
prefix_instrs,
qpx,
recipprec,
secure_plt,
slow_popcntd,
@ -75,7 +76,6 @@ pub const Feature = enum {
pub usingnamespace CpuFeature.feature_set_fns(Feature);
pub const all_features = blk: {
@setEvalBranchQuota(10000);
const len = @typeInfo(Feature).Enum.fields.len;
std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
var result: [len]CpuFeature = undefined;
@ -417,6 +417,13 @@ pub const all_features = blk: {
.power9_altivec,
}),
};
result[@enumToInt(Feature.qpx)] = .{
.llvm_name = null,
.description = "Enable QPX instructions",
.dependencies = featureSet(&[_]Feature{
.fpu,
}),
};
result[@enumToInt(Feature.recipprec)] = .{
.llvm_name = "recipprec",
.description = "Assume higher precision reciprocal estimates",
@ -472,8 +479,8 @@ pub const all_features = blk: {
};
pub const cpu = struct {
pub const @"440" = CpuModel{
.name = "440",
pub const @"ppc440" = CpuModel{
.name = "ppc440",
.llvm_name = "440",
.features = featureSet(&[_]Feature{
.booke,
@ -484,8 +491,8 @@ pub const cpu = struct {
.msync,
}),
};
pub const @"450" = CpuModel{
.name = "450",
pub const @"ppc450" = CpuModel{
.name = "ppc450",
.llvm_name = "450",
.features = featureSet(&[_]Feature{
.booke,
@ -496,70 +503,70 @@ pub const cpu = struct {
.msync,
}),
};
pub const @"601" = CpuModel{
.name = "601",
pub const @"ppc601" = CpuModel{
.name = "ppc601",
.llvm_name = "601",
.features = featureSet(&[_]Feature{
.fpu,
}),
};
pub const @"602" = CpuModel{
.name = "602",
pub const @"ppc602" = CpuModel{
.name = "ppc602",
.llvm_name = "602",
.features = featureSet(&[_]Feature{
.fpu,
}),
};
pub const @"603" = CpuModel{
.name = "603",
pub const @"ppc603" = CpuModel{
.name = "ppc603",
.llvm_name = "603",
.features = featureSet(&[_]Feature{
.fres,
.frsqrte,
}),
};
pub const @"603e" = CpuModel{
.name = "603e",
pub const @"ppc603e" = CpuModel{
.name = "ppc603e",
.llvm_name = "603e",
.features = featureSet(&[_]Feature{
.fres,
.frsqrte,
}),
};
pub const @"603ev" = CpuModel{
.name = "603ev",
pub const @"ppc603ev" = CpuModel{
.name = "ppc603ev",
.llvm_name = "603ev",
.features = featureSet(&[_]Feature{
.fres,
.frsqrte,
}),
};
pub const @"604" = CpuModel{
.name = "604",
pub const @"ppc604" = CpuModel{
.name = "ppc604",
.llvm_name = "604",
.features = featureSet(&[_]Feature{
.fres,
.frsqrte,
}),
};
pub const @"604e" = CpuModel{
.name = "604e",
pub const @"ppc604e" = CpuModel{
.name = "ppc604e",
.llvm_name = "604e",
.features = featureSet(&[_]Feature{
.fres,
.frsqrte,
}),
};
pub const @"620" = CpuModel{
.name = "620",
pub const @"ppc620" = CpuModel{
.name = "ppc620",
.llvm_name = "620",
.features = featureSet(&[_]Feature{
.fres,
.frsqrte,
}),
};
pub const @"7400" = CpuModel{
.name = "7400",
pub const @"ppc7400" = CpuModel{
.name = "ppc7400",
.llvm_name = "7400",
.features = featureSet(&[_]Feature{
.altivec,
@ -567,8 +574,8 @@ pub const cpu = struct {
.frsqrte,
}),
};
pub const @"7450" = CpuModel{
.name = "7450",
pub const @"ppc7450" = CpuModel{
.name = "ppc7450",
.llvm_name = "7450",
.features = featureSet(&[_]Feature{
.altivec,
@ -576,16 +583,16 @@ pub const cpu = struct {
.frsqrte,
}),
};
pub const @"750" = CpuModel{
.name = "750",
pub const @"ppc750" = CpuModel{
.name = "ppc750",
.llvm_name = "750",
.features = featureSet(&[_]Feature{
.fres,
.frsqrte,
}),
};
pub const @"970" = CpuModel{
.name = "970",
pub const @"ppc970" = CpuModel{
.name = "ppc970",
.llvm_name = "970",
.features = featureSet(&[_]Feature{
.@"64bit",
@ -622,6 +629,32 @@ pub const cpu = struct {
.stfiwx,
}),
};
pub const a2q = CpuModel{
.name = "a2q",
.llvm_name = "a2q",
.features = featureSet(&[_]Feature{
.@"64bit",
.booke,
.cmpb,
.fcpsgn,
.fpcvt,
.fprnd,
.fre,
.fres,
.frsqrte,
.frsqrtes,
.fsqrt,
.icbt,
.isel,
.ldbrx,
.lfiwax,
.mfocrf,
.qpx,
.recipprec,
.slow_popcntd,
.stfiwx,
}),
};
pub const e500 = CpuModel{
.name = "e500",
.llvm_name = "e500",

24
lib/std/target/riscv.zig
View File

@ -69,7 +69,6 @@ pub const Feature = enum {
pub usingnamespace CpuFeature.feature_set_fns(Feature);
pub const all_features = blk: {
@setEvalBranchQuota(10000);
const len = @typeInfo(Feature).Enum.fields.len;
std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
var result: [len]CpuFeature = undefined;
@ -382,6 +381,29 @@ pub const all_features = blk: {
};
pub const cpu = struct {
pub const baseline_rv32 = CpuModel{
.name = "baseline_rv32",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.a,
.c,
.d,
.f,
.m,
}),
};
pub const baseline_rv64 = CpuModel{
.name = "baseline_rv64",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.@"64bit",
.a,
.c,
.d,
.f,
.m,
}),
};
pub const generic_rv32 = CpuModel{
.name = "generic_rv32",
.llvm_name = "generic-rv32",

6
lib/std/target/sparc.zig
View File

@ -32,7 +32,6 @@ pub const Feature = enum {
pub usingnamespace CpuFeature.feature_set_fns(Feature);
pub const all_features = blk: {
@setEvalBranchQuota(10000);
const len = @typeInfo(Feature).Enum.fields.len;
std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
var result: [len]CpuFeature = undefined;
@ -161,11 +160,6 @@ pub const cpu = struct {
.llvm_name = "f934",
.features = featureSet(&[_]Feature{}),
};
pub const generic = CpuModel{
.name = "generic",
.llvm_name = "generic",
.features = featureSet(&[_]Feature{}),
};
pub const gr712rc = CpuModel{
.name = "gr712rc",
.llvm_name = "gr712rc",

1
lib/std/target/systemz.zig
View File

@ -49,7 +49,6 @@ pub const Feature = enum {
pub usingnamespace CpuFeature.feature_set_fns(Feature);
pub const all_features = blk: {
@setEvalBranchQuota(10000);
const len = @typeInfo(Feature).Enum.fields.len;
std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
var result: [len]CpuFeature = undefined;

1
lib/std/target/wasm.zig
View File

@ -24,7 +24,6 @@ pub const Feature = enum {
pub usingnamespace CpuFeature.feature_set_fns(Feature);
pub const all_features = blk: {
@setEvalBranchQuota(10000);
const len = @typeInfo(Feature).Enum.fields.len;
std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
var result: [len]CpuFeature = undefined;

20
lib/std/target/x86.zig
View File

@ -8,12 +8,9 @@ const CpuFeature = std.Target.Cpu.Feature;
const CpuModel = std.Target.Cpu.Model;
pub const Feature = enum {
@"16bit_mode",
@"32bit_mode",
@"3dnow",
@"3dnowa",
@"64bit",
@"64bit_mode",
adx,
aes,
amx_bf16,
@ -154,20 +151,9 @@ pub const Feature = enum {
pub usingnamespace CpuFeature.feature_set_fns(Feature);
pub const all_features = blk: {
@setEvalBranchQuota(10000);
const len = @typeInfo(Feature).Enum.fields.len;
std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
var result: [len]CpuFeature = undefined;
result[@enumToInt(Feature.@"16bit_mode")] = .{
.llvm_name = "16bit-mode",
.description = "16-bit mode (i8086)",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.@"32bit_mode")] = .{
.llvm_name = "32bit-mode",
.description = "32-bit mode (80386)",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.@"3dnow")] = .{
.llvm_name = "3dnow",
.description = "Enable 3DNow! instructions",
@ -187,11 +173,6 @@ pub const all_features = blk: {
.description = "Support 64-bit instructions",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.@"64bit_mode")] = .{
.llvm_name = "64bit-mode",
.description = "64-bit mode (x86_64)",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.adx)] = .{
.llvm_name = "adx",
.description = "Support ADX instructions",
@ -1680,7 +1661,6 @@ pub const cpu = struct {
.name = "generic",
.llvm_name = "generic",
.features = featureSet(&[_]Feature{
.@"64bit",
.cx8,
.x87,
}),

6
src/codegen.zig
View File

@ -1689,7 +1689,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
// TODO: add Instruction.supportedOn
// function for ARM
if (Target.arm.featureSetHas(self.target.cpu.features, .armv5t)) {
if (Target.arm.featureSetHas(self.target.cpu.features, .has_v5t)) {
writeInt(u32, try self.code.addManyAsArray(4), Instruction.blx(.al, .lr).toU32());
} else {
writeInt(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, .lr, Instruction.Operand.reg(.pc, Instruction.Operand.Shift.none)).toU32());
@ -2625,7 +2625,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
} else if (Instruction.Operand.fromU32(~@intCast(u32, x))) |op| {
writeInt(u32, try self.code.addManyAsArray(4), Instruction.mvn(.al, reg, op).toU32());
} else if (x <= math.maxInt(u16)) {
if (Target.arm.featureSetHas(self.target.cpu.features, .armv7_a)) {
if (Target.arm.featureSetHas(self.target.cpu.features, .has_v7)) {
writeInt(u32, try self.code.addManyAsArray(4), Instruction.movw(.al, reg, @intCast(u16, x)).toU32());
} else {
writeInt(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, reg, Instruction.Operand.imm(@truncate(u8, x), 0)).toU32());
@ -2634,7 +2634,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
} else {
// TODO write constant to code and load
// relative to pc
if (Target.arm.featureSetHas(self.target.cpu.features, .armv7_a)) {
if (Target.arm.featureSetHas(self.target.cpu.features, .has_v7)) {
// immediate: 0xaaaabbbb
// movw reg, #0xbbbb
// movt reg, #0xaaaa