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aarch64: cleanup register lock

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This commit is contained in:
Jacob Young 2025-11-09 08:08:13 -05:00
parent cbfa87cbea
commit 8647e4d311
4 changed files with 10 additions and 23 deletions
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4
lib/std/Io/Writer.zig
View File

@ -2282,10 +2282,6 @@ pub const Discarding = struct {
pub fn sendFile(w: *Writer, file_reader: *File.Reader, limit: Limit) FileError!usize { pub fn sendFile(w: *Writer, file_reader: *File.Reader, limit: Limit) FileError!usize {
if (File.Handle == void) return error.Unimplemented; if (File.Handle == void) return error.Unimplemented;
switch (builtin.zig_backend) {
else => {},
.stage2_aarch64 => return error.Unimplemented,
}
const d: *Discarding = @alignCast(@fieldParentPtr("writer", w)); const d: *Discarding = @alignCast(@fieldParentPtr("writer", w));
d.count += w.end; d.count += w.end;
w.end = 0; w.end = 0;

1
lib/std/Progress.zig
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@ -427,7 +427,6 @@ const noop_impl = builtin.single_threaded or switch (builtin.os.tag) {
.wasi, .freestanding => true, .wasi, .freestanding => true,
else => false, else => false,
} or switch (builtin.zig_backend) { } or switch (builtin.zig_backend) {
.stage2_aarch64 => true,
else => false, else => false,
}; };

5
lib/std/fs/File.zig
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@ -739,10 +739,7 @@ pub const Writer = struct {
return .{ return .{
.vtable = &.{ .vtable = &.{
.drain = drain, .drain = drain,
.sendFile = switch (builtin.zig_backend) { .sendFile = sendFile,
else => sendFile,
.stage2_aarch64 => Io.Writer.unimplementedSendFile,
},
}, },
.buffer = buffer, .buffer = buffer,
}; };

23
src/codegen/aarch64/Select.zig
View File

@ -9570,11 +9570,15 @@ pub const Value = struct {
.zr .zr
else else
return false; return false;
if (part_ra != .zr) { const part_lock: RegLock = switch (part_ra) {
const live_vi = isel.live_registers.getPtr(part_ra); else => isel.lockReg(part_ra),
assert(live_vi.* == .free); .zr => .empty,
live_vi.* = .allocating; };
} defer switch (opts.expected_live_registers.get(part_ra)) {
_ => {},
.allocating => unreachable,
.free => part_lock.unlock(isel),
};
if (opts.wrap) |int_info| switch (int_info.bits) { if (opts.wrap) |int_info| switch (int_info.bits) {
else => unreachable, else => unreachable,
1...7, 9...15, 17...31 => |bits| try isel.emit(switch (int_info.signedness) { 1...7, 9...15, 17...31 => |bits| try isel.emit(switch (int_info.signedness) {
@ -9605,15 +9609,6 @@ pub const Value = struct {
64 => {}, 64 => {},
}; };
try isel.loadReg(part_ra, part_size, part_vi.signedness(isel), base_ra, opts.offset); try isel.loadReg(part_ra, part_size, part_vi.signedness(isel), base_ra, opts.offset);
if (part_ra != .zr) {
const live_vi = isel.live_registers.getPtr(part_ra);
assert(live_vi.* == .allocating);
switch (opts.expected_live_registers.get(part_ra)) {
_ => {},
.allocating => unreachable,
.free => live_vi.* = .free,
}
}
return true; return true;
} }
var used = false; var used = false;