diff --git a/lib/std/Io/Writer.zig b/lib/std/Io/Writer.zig index d0721307d4..0dc7923f05 100644 --- a/lib/std/Io/Writer.zig +++ b/lib/std/Io/Writer.zig @@ -2282,10 +2282,6 @@ pub const Discarding = struct { pub fn sendFile(w: *Writer, file_reader: *File.Reader, limit: Limit) FileError!usize { if (File.Handle == void) return error.Unimplemented; - switch (builtin.zig_backend) { - else => {}, - .stage2_aarch64 => return error.Unimplemented, - } const d: *Discarding = @alignCast(@fieldParentPtr("writer", w)); d.count += w.end; w.end = 0; diff --git a/lib/std/Progress.zig b/lib/std/Progress.zig index d2e962a8c2..2e4fe2963d 100644 --- a/lib/std/Progress.zig +++ b/lib/std/Progress.zig @@ -427,7 +427,6 @@ const noop_impl = builtin.single_threaded or switch (builtin.os.tag) { .wasi, .freestanding => true, else => false, } or switch (builtin.zig_backend) { - .stage2_aarch64 => true, else => false, }; diff --git a/lib/std/fs/File.zig b/lib/std/fs/File.zig index 11d8e7471b..073ab6777b 100644 --- a/lib/std/fs/File.zig +++ b/lib/std/fs/File.zig @@ -739,10 +739,7 @@ pub const Writer = struct { return .{ .vtable = &.{ .drain = drain, - .sendFile = switch (builtin.zig_backend) { - else => sendFile, - .stage2_aarch64 => Io.Writer.unimplementedSendFile, - }, + .sendFile = sendFile, }, .buffer = buffer, }; diff --git a/src/codegen/aarch64/Select.zig b/src/codegen/aarch64/Select.zig index 4fe798271f..aa96cf9437 100644 --- a/src/codegen/aarch64/Select.zig +++ b/src/codegen/aarch64/Select.zig @@ -9570,11 +9570,15 @@ pub const Value = struct { .zr else return false; - if (part_ra != .zr) { - const live_vi = isel.live_registers.getPtr(part_ra); - assert(live_vi.* == .free); - live_vi.* = .allocating; - } + const part_lock: RegLock = switch (part_ra) { + else => isel.lockReg(part_ra), + .zr => .empty, + }; + defer switch (opts.expected_live_registers.get(part_ra)) { + _ => {}, + .allocating => unreachable, + .free => part_lock.unlock(isel), + }; if (opts.wrap) |int_info| switch (int_info.bits) { else => unreachable, 1...7, 9...15, 17...31 => |bits| try isel.emit(switch (int_info.signedness) { @@ -9605,15 +9609,6 @@ pub const Value = struct { 64 => {}, }; try isel.loadReg(part_ra, part_size, part_vi.signedness(isel), base_ra, opts.offset); - if (part_ra != .zr) { - const live_vi = isel.live_registers.getPtr(part_ra); - assert(live_vi.* == .allocating); - switch (opts.expected_live_registers.get(part_ra)) { - _ => {}, - .allocating => unreachable, - .free => live_vi.* = .free, - } - } return true; } var used = false;