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https://github.com/ziglang/zig.git
synced 2026-02-09 11:03:30 +00:00
x64: pull shl and shr into one helper fn
This commit is contained in:
Jakub Konka
parent
aef3c149e6
commit
6a4e445f5a
@ -597,7 +597,7 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void {
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.mul_sat => try self.airMulSat(inst),
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.rem => try self.airMulDivBinOp(inst),
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.mod => try self.airMulDivBinOp(inst),
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.shl, .shl_exact => try self.airShl(inst),
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.shl, .shl_exact => try self.airShlShrBinOp(inst),
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.shl_sat => try self.airShlSat(inst),
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.min => try self.airMin(inst),
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.max => try self.airMax(inst),
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@ -643,7 +643,7 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void {
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.bit_and => try self.airBinOp(inst),
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.bit_or => try self.airBinOp(inst),
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.xor => try self.airBinOp(inst),
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.shr, .shr_exact => try self.airShr(inst),
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.shr, .shr_exact => try self.airShlShrBinOp(inst),
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.alloc => try self.airAlloc(inst),
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.ret_ptr => try self.airRetPtr(inst),
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@ -1652,64 +1652,22 @@ fn genInlineIntDivFloor(self: *Self, ty: Type, lhs: MCValue, rhs: MCValue) !MCVa
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return MCValue{ .register = divisor };
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}
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fn airShl(self: *Self, inst: Air.Inst.Index) !void {
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fn airShlShrBinOp(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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if (self.liveness.isUnused(inst)) {
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return self.finishAir(inst, .dead, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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const ty = self.air.typeOfIndex(inst);
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const tag = self.air.instructions.items(.tag)[inst];
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switch (tag) {
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.shl_exact => return self.fail("TODO implement {} for type {}", .{ tag, ty.fmtDebug() }),
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.shl => {},
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else => unreachable,
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}
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const lhs = try self.resolveInst(bin_op.lhs);
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const rhs = try self.resolveInst(bin_op.rhs);
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const lhs_ty = self.air.typeOf(bin_op.lhs);
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const rhs_ty = self.air.typeOf(bin_op.rhs);
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if (ty.zigTypeTag() != .Int) {
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return self.fail("TODO implement .shl for type {}", .{ty.fmtDebug()});
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}
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if (ty.abiSize(self.target.*) > 8) {
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return self.fail("TODO implement .shl for integers larger than 8 bytes", .{});
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}
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const result = try self.genShiftBinOp(tag, inst, lhs, rhs, lhs_ty, rhs_ty);
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// TODO look into reusing the operands
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// TODO audit register allocation mechanics
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const shift = try self.resolveInst(bin_op.rhs);
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const shift_ty = self.air.typeOf(bin_op.rhs);
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blk: {
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switch (shift) {
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.register => |reg| {
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if (reg.to64() == .rcx) break :blk;
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},
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else => {},
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}
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try self.register_manager.getReg(.rcx, null);
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try self.genSetReg(shift_ty, .rcx, shift);
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}
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const rcx_lock = self.register_manager.lockRegAssumeUnused(.rcx);
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defer self.register_manager.unlockReg(rcx_lock);
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const value = try self.resolveInst(bin_op.lhs);
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const value_lock: ?RegisterLock = switch (value) {
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.register => |reg| self.register_manager.lockRegAssumeUnused(reg),
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else => null,
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};
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defer if (value_lock) |lock| self.register_manager.unlockReg(lock);
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const dst_mcv = try self.copyToRegisterWithInstTracking(inst, ty, value);
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_ = try self.addInst(.{
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.tag = .sal,
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.ops = (Mir.Ops{
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.reg1 = dst_mcv.register,
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.flags = 0b01,
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}).encode(),
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.data = undefined,
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});
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return self.finishAir(inst, dst_mcv, .{ bin_op.lhs, bin_op.rhs, .none });
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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fn airShlSat(self: *Self, inst: Air.Inst.Index) !void {
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@ -1721,80 +1679,6 @@ fn airShlSat(self: *Self, inst: Air.Inst.Index) !void {
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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fn airShr(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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if (self.liveness.isUnused(inst)) {
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return self.finishAir(inst, .dead, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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const ty = self.air.typeOfIndex(inst);
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const tag = self.air.instructions.items(.tag)[inst];
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switch (tag) {
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.shr_exact => return self.fail("TODO implement shr_exact for type {}", .{ty.fmtDebug()}),
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.shr => {},
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else => unreachable,
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}
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if (ty.zigTypeTag() != .Int) {
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return self.fail("TODO implement shr for type {}", .{ty.fmtDebug()});
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}
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if (ty.abiSize(self.target.*) > 8) {
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return self.fail("TODO implement shr for integers larger than 8 bytes", .{});
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}
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// TODO look into reusing the operands
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// TODO audit register allocation mechanics
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const shift = try self.resolveInst(bin_op.rhs);
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const shift_ty = self.air.typeOf(bin_op.rhs);
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blk: {
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switch (shift) {
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.register => |reg| {
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if (reg.to64() == .rcx) break :blk;
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},
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else => {},
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}
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try self.register_manager.getReg(.rcx, null);
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try self.genSetReg(shift_ty, .rcx, shift);
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}
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const rcx_lock = self.register_manager.lockRegAssumeUnused(.rcx);
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defer self.register_manager.unlockReg(rcx_lock);
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const value = try self.resolveInst(bin_op.lhs);
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const value_lock: ?RegisterLock = switch (value) {
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.register => |reg| self.register_manager.lockRegAssumeUnused(reg),
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else => null,
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};
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defer if (value_lock) |lock| self.register_manager.unlockReg(lock);
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const dst_mcv = try self.copyToRegisterWithInstTracking(inst, ty, value);
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switch (ty.intInfo(self.target.*).signedness) {
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.signed => {
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_ = try self.addInst(.{
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.tag = .sar,
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.ops = (Mir.Ops{
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.reg1 = dst_mcv.register,
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.flags = 0b01,
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}).encode(),
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.data = undefined,
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});
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},
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.unsigned => {
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_ = try self.addInst(.{
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.tag = .shr,
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.ops = (Mir.Ops{
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.reg1 = dst_mcv.register,
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.flags = 0b01,
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}).encode(),
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.data = undefined,
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});
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},
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}
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return self.finishAir(inst, dst_mcv, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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fn airOptionalPayload(self: *Self, inst: Air.Inst.Index) !void {
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const ty_op = self.air.instructions.items(.data)[inst].ty_op;
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if (self.liveness.isUnused(inst)) {
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@ -1822,7 +1706,7 @@ fn airOptionalPayload(self: *Self, inst: Air.Inst.Index) !void {
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// TODO reuse the operand
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const result = try self.copyToRegisterWithInstTracking(inst, optional_ty, operand);
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const shift = @intCast(u8, offset * @sizeOf(usize));
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try self.shiftRegister(result.register, @intCast(u8, shift));
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try self.shiftRegisterRightUnsigned(result.register, @intCast(u8, shift));
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break :result result;
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},
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else => return self.fail("TODO implement optional_payload when operand is {}", .{operand}),
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@ -1909,7 +1793,7 @@ fn airUnwrapErrPayload(self: *Self, inst: Air.Inst.Index) !void {
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// TODO reuse operand
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const shift = @intCast(u6, err_abi_size * @sizeOf(usize));
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const result = try self.copyToRegisterWithInstTracking(inst, err_union_ty, operand);
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try self.shiftRegister(result.register.to64(), shift);
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try self.shiftRegisterRightUnsigned(result.register.to64(), shift);
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break :result MCValue{
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.register = registerAlias(result.register, @intCast(u32, payload_ty.abiSize(self.target.*))),
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};
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@ -2421,7 +2305,7 @@ fn airGetUnionTag(self: *Self, inst: Air.Inst.Index) !void {
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else
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0;
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const result = try self.copyToRegisterWithInstTracking(inst, union_ty, operand);
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try self.shiftRegister(result.register.to64(), shift);
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try self.shiftRegisterRightUnsigned(result.register.to64(), shift);
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break :blk MCValue{
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.register = registerAlias(result.register, @intCast(u32, layout.tag_size)),
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};
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@ -3020,7 +2904,7 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void {
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// Shift by struct_field_offset.
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const shift = @intCast(u8, struct_field_offset * @sizeOf(usize));
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try self.shiftRegister(dst_mcv.register, shift);
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try self.shiftRegisterRightUnsigned(dst_mcv.register, shift);
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// Mask with reg.size() - struct_field_size
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const max_reg_bit_width = Register.rax.size();
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@ -3097,7 +2981,111 @@ fn airFieldParentPtr(self: *Self, inst: Air.Inst.Index) !void {
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}
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/// Result is always a register.
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/// Clobbers .rax and .rdx therefore care needs to be taken to spill operands upfront.
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/// Clobbers .rcx therefore care is needed to spill .rcx upfront.
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/// Asserts .rcx is free.
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fn genShiftBinOp(
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self: *Self,
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tag: Air.Inst.Tag,
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maybe_inst: ?Air.Inst.Index,
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lhs: MCValue,
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rhs: MCValue,
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lhs_ty: Type,
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rhs_ty: Type,
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) !MCValue {
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if (lhs_ty.zigTypeTag() == .Vector or lhs_ty.zigTypeTag() == .Float) {
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return self.fail("TODO implement genShiftBinOp for {}", .{lhs_ty.fmtDebug()});
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}
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if (lhs_ty.abiSize(self.target.*) > 8) {
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return self.fail("TODO implement genShiftBinOp for {}", .{lhs_ty.fmtDebug()});
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}
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assert(self.register_manager.isRegFree(.rcx));
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try self.register_manager.getReg(.rcx, null);
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try self.genSetReg(rhs_ty, .rcx, rhs);
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const rcx_lock = self.register_manager.lockRegAssumeUnused(.rcx);
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defer self.register_manager.unlockReg(rcx_lock);
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const int_info = lhs_ty.intInfo(self.target.*);
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const signedness = int_info.signedness;
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const lhs_lock: ?RegisterLock = switch (lhs) {
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.register => |reg| self.register_manager.lockReg(reg),
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else => null,
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};
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defer if (lhs_lock) |lock| self.register_manager.unlockReg(lock);
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const rhs_lock: ?RegisterLock = switch (rhs) {
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.register => |reg| self.register_manager.lockReg(reg),
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else => null,
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};
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defer if (rhs_lock) |lock| self.register_manager.unlockReg(lock);
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const dst: MCValue = blk: {
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if (maybe_inst) |inst| {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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// TODO dst can also be a memory location
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if (self.reuseOperand(inst, bin_op.lhs, 0, lhs) and lhs.isRegister()) {
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break :blk lhs;
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}
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break :blk try self.copyToRegisterWithInstTracking(inst, lhs_ty, lhs);
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}
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break :blk MCValue{ .register = try self.copyToTmpRegister(lhs_ty, lhs) };
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};
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switch (tag) {
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.shl => switch (signedness) {
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.signed => {
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_ = try self.addInst(.{
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.tag = .sal,
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.ops = (Mir.Ops{
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.reg1 = dst.register,
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.flags = 0b01,
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}).encode(),
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.data = undefined,
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});
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},
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.unsigned => {
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_ = try self.addInst(.{
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.tag = .shl,
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.ops = (Mir.Ops{
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.reg1 = dst.register,
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.flags = 0b01,
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}).encode(),
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.data = undefined,
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});
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},
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},
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.shr => switch (signedness) {
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.signed => {
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_ = try self.addInst(.{
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.tag = .sar,
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.ops = (Mir.Ops{
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.reg1 = dst.register,
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.flags = 0b01,
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}).encode(),
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.data = undefined,
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});
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},
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.unsigned => {
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_ = try self.addInst(.{
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.tag = .shr,
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.ops = (Mir.Ops{
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.reg1 = dst.register,
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.flags = 0b01,
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}).encode(),
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.data = undefined,
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});
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},
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},
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else => unreachable,
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}
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return dst;
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}
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/// Result is always a register.
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/// Clobbers .rax and .rdx therefore care is needed to spill .rax and .rdx upfront.
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/// Asserts .rax and .rdx are free.
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fn genMulDivBinOp(
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self: *Self,
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@ -6790,7 +6778,8 @@ fn registerAlias(reg: Register, size_bytes: u32) Register {
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}
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}
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fn shiftRegister(self: *Self, reg: Register, shift: u8) !void {
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/// Shifts register right without sign-extension.
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fn shiftRegisterRightUnsigned(self: *Self, reg: Register, shift: u8) !void {
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if (shift == 0) return;
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if (shift == 1) {
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_ = try self.addInst(.{
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