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stage2: sparc64: Use official encoding for not rs2, rs1

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This commit is contained in:
Koakuma 2022-06-13 00:27:51 +07:00
parent e7fde5f64e
commit 5c8612642b
2 changed files with 4 additions and 3 deletions
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2
src/arch/sparc64/Emit.zig
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@ -203,7 +203,7 @@ fn mirArithmetic2Op(emit: *Emit, inst: Mir.Inst.Index) !void {
.@"return" => try emit.writeInstruction(Instruction.@"return"(Register, rs1, rs2)),
.cmp => try emit.writeInstruction(Instruction.subcc(Register, rs1, rs2, .g0)),
.mov => try emit.writeInstruction(Instruction.@"or"(Register, .g0, rs2, rs1)),
.not => try emit.writeInstruction(Instruction.xnor(Register, .g0, rs2, rs1)),
.not => try emit.writeInstruction(Instruction.xnor(Register, rs2, .g0, rs1)),
else => unreachable,
}
}

5
src/arch/sparc64/Mir.zig
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@ -158,8 +158,9 @@ pub const Inst = struct {
/// This uses the arithmetic_2op field, with rs1
/// being the *destination* register.
// TODO is it okay to abuse rs1 in this way?
// TODO this differs from official encoding for convenience, fix it later
not, // not rs2/imm, rs1 -> xnor %g0, rs2/imm, rs1
// not rs2, rs1 -> xnor rs2, %g0, rs1
// not imm, rs1 -> xnor %g0, imm, rs1
not,
};
/// The position of an MIR instruction within the `Mir` instructions array.