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stage2: sparc64: Introduce condition_register MCValue type
Introduce condition_register MCValue type for future uses with BPr/MOVr (mostly when needing to compare a signed value with zero)
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Koakuma
parent
accc3bad63
commit
e7fde5f64e
@ -96,6 +96,9 @@ stack: std.AutoHashMapUnmanaged(u32, StackAllocation) = .{},
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/// Tracks the current instruction allocated to the condition flags
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condition_flags_inst: ?Air.Inst.Index = null,
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/// Tracks the current instruction allocated to the condition register
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condition_register_inst: ?Air.Inst.Index = null,
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/// Offset from the stack base, representing the end of the stack frame.
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max_end_stack: u32 = 0,
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/// Represents the current end stack offset. If there is no existing slot
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@ -148,6 +151,13 @@ const MCValue = union(enum) {
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cond: Instruction.Condition,
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ccr: Instruction.CCR,
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},
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/// The value is in the specified Register. The value is 1 (if
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/// the type is u1) or true (if the type in bool) iff the
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/// specified condition is true.
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condition_register: struct {
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cond: Instruction.RCondition,
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reg: Register,
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},
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fn isMemory(mcv: MCValue) bool {
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return switch (mcv) {
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@ -171,6 +181,8 @@ const MCValue = union(enum) {
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.immediate,
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.memory,
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.condition_flags,
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.condition_register,
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.ptr_stack_offset,
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.undef,
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=> false,
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@ -1748,7 +1760,7 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void {
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_ = try self.addInst(.{
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.tag = .movcc,
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.data = .{
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.conditional_move = .{
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.conditional_move_int = .{
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.ccr = rwo.flag.ccr,
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.cond = .{ .icond = rwo.flag.cond },
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.is_imm = true,
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@ -2401,6 +2413,17 @@ fn condBr(self: *Self, condition: MCValue) !Mir.Inst.Index {
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},
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},
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}),
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.condition_register => |reg| try self.addInst(.{
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.tag = .bpr,
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.data = .{
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.branch_predict_reg = .{
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.rs1 = reg.reg,
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// Here we map to the opposite condition because the jump is to the false branch.
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.cond = reg.cond.negate(),
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.inst = undefined, // Will be filled by performReloc
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},
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},
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}),
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else => blk: {
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const reg = switch (condition) {
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.register => |r| r,
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@ -2655,7 +2678,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
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_ = try self.addInst(.{
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.tag = .movcc,
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.data = .{
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.conditional_move = .{
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.conditional_move_int = .{
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.ccr = ccr,
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.cond = condition,
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.is_imm = true,
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@ -2665,6 +2688,34 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
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},
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});
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},
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.condition_register => |op| {
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const condition = op.cond;
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const register = op.reg;
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_ = try self.addInst(.{
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.tag = .mov,
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.data = .{
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.arithmetic_2op = .{
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.is_imm = false,
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.rs1 = reg,
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.rs2_or_imm = .{ .rs2 = .g0 },
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},
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},
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});
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_ = try self.addInst(.{
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.tag = .movr,
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.data = .{
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.conditional_move_reg = .{
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.cond = condition,
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.is_imm = true,
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.rd = reg,
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.rs1 = register,
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.rs2_or_imm = .{ .imm = 1 },
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},
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},
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});
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},
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.undef => {
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if (!self.wantSafety())
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return; // The already existing value will do just fine.
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@ -2832,6 +2883,7 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
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}
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},
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.condition_flags,
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.condition_register,
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.immediate,
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.ptr_stack_offset,
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=> {
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@ -2872,7 +2924,7 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
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_ = try self.addInst(.{
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.tag = .movcc,
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.data = .{
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.conditional_move = .{
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.conditional_move_int = .{
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.ccr = rwo.flag.ccr,
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.cond = .{ .icond = rwo.flag.cond },
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.is_imm = true,
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@ -3124,6 +3176,7 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
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.unreach => unreachable,
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.dead => unreachable,
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.condition_flags,
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.condition_register,
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.register_with_overflow,
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=> unreachable, // cannot hold an address
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.immediate => |imm| try self.setRegOrMem(elem_ty, dst_mcv, .{ .memory = imm }),
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@ -3475,6 +3528,7 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type
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.unreach => unreachable,
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.dead => unreachable,
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.condition_flags,
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.condition_register,
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.register_with_overflow,
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=> unreachable, // cannot hold an address
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.immediate => |imm| {
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@ -99,6 +99,8 @@ pub fn emitMir(
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.movcc => try emit.mirConditionalMove(inst),
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.movr => @panic("TODO implement sparc64 movr"),
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.mulx => try emit.mirArithmetic3Op(inst),
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.nop => try emit.mirNop(),
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@ -314,7 +316,7 @@ fn mirConditionalMove(emit: *Emit, inst: Mir.Inst.Index) !void {
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switch (tag) {
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.movcc => {
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const data = emit.mir.instructions.items(.data)[inst].conditional_move;
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const data = emit.mir.instructions.items(.data)[inst].conditional_move_int;
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if (data.is_imm) {
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try emit.writeInstruction(Instruction.movcc(
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i11,
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@ -78,9 +78,13 @@ pub const Inst = struct {
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xnor,
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/// A.35 Move Integer Register on Condition (MOVcc)
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/// This uses the conditional_move field.
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/// This uses the conditional_move_int field.
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movcc,
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/// A.36 Move Integer Register on Register Condition (MOVr)
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/// This uses the conditional_move_reg field.
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movr,
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/// A.37 Multiply and Divide (64-bit)
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/// This uses the arithmetic_3op field.
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// TODO add other operations.
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@ -230,12 +234,12 @@ pub const Inst = struct {
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inst: Index,
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},
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/// Conditional move.
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/// Conditional move, checking the integer status code
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/// if is_imm true then it uses the imm field of rs2_or_imm,
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/// otherwise it uses rs2 field.
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///
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/// Used by e.g. movcc
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conditional_move: struct {
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conditional_move_int: struct {
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is_imm: bool,
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ccr: Instruction.CCR,
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cond: Instruction.Condition,
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@ -246,6 +250,22 @@ pub const Inst = struct {
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},
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},
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/// Conditional move, comparing a register's content with zero
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/// if is_imm true then it uses the imm field of rs2_or_imm,
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/// otherwise it uses rs2 field.
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///
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/// Used by e.g. movr
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conditional_move_reg: struct {
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is_imm: bool,
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cond: Instruction.RCondition,
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rd: Register,
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rs1: Register,
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rs2_or_imm: union {
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rs2: Register,
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imm: i10,
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},
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},
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/// No additional data
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///
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/// Used by e.g. flushw
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@ -475,6 +475,21 @@ pub const Instruction = union(enum) {
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ne_zero,
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gt_zero,
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ge_zero,
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/// Returns the condition which is true iff the given condition is
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/// false (if such a condition exists).
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pub fn negate(cond: RCondition) RCondition {
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return switch (cond) {
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.eq_zero => .ne_zero,
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.ne_zero => .eq_zero,
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.lt_zero => .ge_zero,
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.ge_zero => .lt_zero,
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.le_zero => .gt_zero,
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.gt_zero => .le_zero,
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.reserved1 => unreachable,
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.reserved2 => unreachable,
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};
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}
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};
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pub const ASI = enum(u8) {
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