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https://github.com/ziglang/zig.git
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x64: impl airMemcpy using inline memcpy
This commit is contained in:
Jakub Konka
parent
ca97caab8a
commit
5a6f4395e6
@ -2346,7 +2346,7 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
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return self.genSetStack(elem_ty, off, MCValue{ .register = tmp_reg }, .{});
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}
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try self.genInlineMemcpy(off, elem_ty, ptr, .{});
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try self.genInlineMemcpy(dst_mcv, ptr, .{ .immediate = abi_size }, .{});
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},
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else => return self.fail("TODO implement loading from register into {}", .{dst_mcv}),
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}
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@ -2392,6 +2392,7 @@ fn loadMemPtrIntoRegister(self: *Self, reg: Register, ptr_ty: Type, ptr: MCValue
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.got_load,
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.direct_load,
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=> |sym_index| {
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const abi_size = @intCast(u32, ptr_ty.abiSize(self.target.*));
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const flags: u2 = switch (ptr) {
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.got_load => 0b00,
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.direct_load => 0b01,
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@ -2400,7 +2401,7 @@ fn loadMemPtrIntoRegister(self: *Self, reg: Register, ptr_ty: Type, ptr: MCValue
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_ = try self.addInst(.{
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.tag = .lea_pie,
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.ops = (Mir.Ops{
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.reg1 = registerAlias(reg, @intCast(u32, ptr_ty.abiSize(self.target.*))),
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.reg1 = registerAlias(reg, abi_size),
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.flags = flags,
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}).encode(),
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.data = .{
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@ -2524,7 +2525,7 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type
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return self.store(ptr, .{ .register = tmp_reg }, ptr_ty, value_ty);
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}
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try self.genInlineMemcpy(0, value_ty, value, .{
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try self.genInlineMemcpy(.{ .stack_offset = 0 }, value, .{ .immediate = abi_size }, .{
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.source_stack_base = .rbp,
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.dest_stack_base = reg.to64(),
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});
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@ -3464,7 +3465,7 @@ fn airRetLoad(self: *Self, inst: Air.Inst.Index) !void {
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.data = undefined,
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});
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try self.ret_backpatches.append(self.gpa, backpatch);
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try self.genInlineMemcpy(0, elem_ty, ptr, .{
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try self.genInlineMemcpy(.{ .stack_offset = 0 }, ptr, .{ .immediate = elem_ty.abiSize(self.target.*) }, .{
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.source_stack_base = .rbp,
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.dest_stack_base = reg,
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});
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@ -4469,7 +4470,7 @@ fn genSetStackArg(self: *Self, ty: Type, stack_offset: i32, mcv: MCValue) InnerE
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return self.genSetStackArg(ty, stack_offset, MCValue{ .register = reg });
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}
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try self.genInlineMemcpy(stack_offset, ty, mcv, .{
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try self.genInlineMemcpy(.{ .stack_offset = stack_offset }, mcv, .{ .immediate = abi_size }, .{
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.source_stack_base = .rbp,
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.dest_stack_base = .rsp,
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});
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@ -4495,7 +4496,7 @@ fn genSetStackArg(self: *Self, ty: Type, stack_offset: i32, mcv: MCValue) InnerE
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return self.genSetStackArg(ty, stack_offset, MCValue{ .register = reg });
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}
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try self.genInlineMemcpy(stack_offset, ty, mcv, .{
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try self.genInlineMemcpy(.{ .stack_offset = stack_offset }, mcv, .{ .immediate = abi_size }, .{
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.source_stack_base = .rbp,
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.dest_stack_base = .rsp,
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});
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@ -4650,7 +4651,7 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: i32, mcv: MCValue, opts: Inl
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return self.genSetStack(ty, stack_offset, MCValue{ .register = reg }, opts);
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}
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try self.genInlineMemcpy(stack_offset, ty, mcv, opts);
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try self.genInlineMemcpy(.{ .stack_offset = stack_offset }, mcv, .{ .immediate = abi_size }, opts);
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},
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.ptr_stack_offset => {
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const reg = try self.copyToTmpRegister(ty, mcv);
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@ -4667,7 +4668,7 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: i32, mcv: MCValue, opts: Inl
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return self.genSetStack(ty, stack_offset, MCValue{ .register = reg }, opts);
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}
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try self.genInlineMemcpy(stack_offset, ty, mcv, opts);
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try self.genInlineMemcpy(.{ .stack_offset = stack_offset }, mcv, .{ .immediate = abi_size }, opts);
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},
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}
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}
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@ -4677,9 +4678,13 @@ const InlineMemcpyOpts = struct {
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dest_stack_base: ?Register = null,
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};
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fn genInlineMemcpy(self: *Self, stack_offset: i32, ty: Type, val: MCValue, opts: InlineMemcpyOpts) InnerError!void {
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const abi_size = ty.abiSize(self.target.*);
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fn genInlineMemcpy(
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self: *Self,
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dst_ptr: MCValue,
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src_ptr: MCValue,
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len: MCValue,
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opts: InlineMemcpyOpts,
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) InnerError!void {
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// TODO this is wrong. We should check first if any of the operands is in `.rax` or `.rcx` before
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// spilling. Consolidate with other TODOs regarding register allocation mechanics.
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try self.register_manager.getReg(.rax, null);
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@ -4694,19 +4699,55 @@ fn genInlineMemcpy(self: *Self, stack_offset: i32, ty: Type, val: MCValue, opts:
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if (opts.dest_stack_base) |reg| self.register_manager.freezeRegs(&.{reg});
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defer if (opts.dest_stack_base) |reg| self.register_manager.unfreezeRegs(&.{reg});
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const addr_reg = try self.register_manager.allocReg(null);
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switch (val) {
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const dst_addr_reg = try self.register_manager.allocReg(null);
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switch (dst_ptr) {
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.got_load => unreachable,
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.memory,
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.direct_load,
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.got_load,
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=> {
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try self.loadMemPtrIntoRegister(addr_reg, Type.usize, val);
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try self.loadMemPtrIntoRegister(dst_addr_reg, Type.usize, dst_ptr);
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},
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.ptr_stack_offset, .stack_offset => |off| {
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_ = try self.addInst(.{
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.tag = .lea,
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.ops = (Mir.Ops{
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.reg1 = addr_reg.to64(),
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.reg1 = dst_addr_reg.to64(),
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.reg2 = opts.dest_stack_base orelse .rbp,
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}).encode(),
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.data = .{ .imm = @bitCast(u32, -off) },
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});
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},
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.register => |reg| {
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_ = try self.addInst(.{
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.tag = .mov,
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.ops = (Mir.Ops{
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.reg1 = registerAlias(dst_addr_reg, @divExact(reg.size(), 8)),
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.reg2 = reg,
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}).encode(),
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.data = undefined,
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});
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},
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else => {
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return self.fail("TODO implement memcpy for setting stack when dest is {}", .{dst_ptr});
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},
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}
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self.register_manager.freezeRegs(&.{dst_addr_reg});
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defer self.register_manager.unfreezeRegs(&.{dst_addr_reg});
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const src_addr_reg = try self.register_manager.allocReg(null);
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switch (src_ptr) {
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.got_load => unreachable,
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.memory,
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.direct_load,
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=> {
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try self.loadMemPtrIntoRegister(src_addr_reg, Type.usize, src_ptr);
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},
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.ptr_stack_offset, .stack_offset => |off| {
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_ = try self.addInst(.{
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.tag = .lea,
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.ops = (Mir.Ops{
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.reg1 = src_addr_reg.to64(),
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.reg2 = opts.source_stack_base orelse .rbp,
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}).encode(),
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.data = .{ .imm = @bitCast(u32, -off) },
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@ -4716,25 +4757,25 @@ fn genInlineMemcpy(self: *Self, stack_offset: i32, ty: Type, val: MCValue, opts:
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_ = try self.addInst(.{
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.tag = .mov,
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.ops = (Mir.Ops{
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.reg1 = registerAlias(addr_reg, @divExact(reg.size(), 8)),
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.reg1 = registerAlias(src_addr_reg, @divExact(reg.size(), 8)),
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.reg2 = reg,
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}).encode(),
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.data = undefined,
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});
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},
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else => {
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return self.fail("TODO implement memcpy for setting stack from {}", .{val});
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return self.fail("TODO implement memcpy for setting stack when src is {}", .{src_ptr});
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},
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}
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self.register_manager.freezeRegs(&.{addr_reg});
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defer self.register_manager.unfreezeRegs(&.{addr_reg});
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self.register_manager.freezeRegs(&.{src_addr_reg});
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defer self.register_manager.unfreezeRegs(&.{src_addr_reg});
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const regs = try self.register_manager.allocRegs(2, .{ null, null });
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const count_reg = regs[0].to64();
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const tmp_reg = regs[1].to8();
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try self.genSetReg(Type.u32, count_reg, .{ .immediate = @intCast(u32, abi_size) });
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try self.genSetReg(Type.usize, count_reg, len);
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// mov rcx, 0
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_ = try self.addInst(.{
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@ -4776,7 +4817,7 @@ fn genInlineMemcpy(self: *Self, stack_offset: i32, ty: Type, val: MCValue, opts:
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.tag = .mov_scale_src,
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.ops = (Mir.Ops{
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.reg1 = tmp_reg.to8(),
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.reg2 = addr_reg,
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.reg2 = src_addr_reg,
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}).encode(),
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.data = .{ .imm = 0 },
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});
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@ -4785,10 +4826,10 @@ fn genInlineMemcpy(self: *Self, stack_offset: i32, ty: Type, val: MCValue, opts:
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_ = try self.addInst(.{
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.tag = .mov_scale_dst,
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.ops = (Mir.Ops{
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.reg1 = opts.dest_stack_base orelse .rbp,
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.reg1 = dst_addr_reg,
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.reg2 = tmp_reg.to8(),
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}).encode(),
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.data = .{ .imm = @bitCast(u32, -stack_offset) },
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.data = .{ .imm = 0 },
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});
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// add rcx, 1
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@ -5076,33 +5117,15 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
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.data = undefined,
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});
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},
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.got_load,
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.direct_load,
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=> |sym_index| {
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const flags: u2 = switch (mcv) {
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.got_load => 0b00,
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.direct_load => 0b01,
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else => unreachable,
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};
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_ = try self.addInst(.{
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.tag = .lea_pie,
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.ops = (Mir.Ops{
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.reg1 = reg,
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.flags = flags,
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}).encode(),
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.data = .{
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.load_reloc = .{
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.atom_index = self.mod_fn.owner_decl.link.macho.local_sym_index,
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.sym_index = sym_index,
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},
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},
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});
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// MOV reg, [reg]
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.got_load,
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=> {
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try self.loadMemPtrIntoRegister(reg, Type.usize, mcv);
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_ = try self.addInst(.{
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.tag = .mov,
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.ops = (Mir.Ops{
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.reg1 = reg,
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.reg2 = reg,
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.reg1 = reg.to64(),
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.reg2 = reg.to64(),
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.flags = 0b01,
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}).encode(),
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.data = .{ .imm = 0 },
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@ -5283,8 +5306,25 @@ fn airMemset(self: *Self, inst: Air.Inst.Index) !void {
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}
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fn airMemcpy(self: *Self, inst: Air.Inst.Index) !void {
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_ = inst;
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return self.fail("TODO implement airMemcpy for {}", .{self.target.cpu.arch});
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const pl_op = self.air.instructions.items(.data)[inst].pl_op;
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const extra = self.air.extraData(Air.Bin, pl_op.payload).data;
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const dst_ptr = try self.resolveInst(pl_op.operand);
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dst_ptr.freezeIfRegister(&self.register_manager);
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defer dst_ptr.unfreezeIfRegister(&self.register_manager);
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const src_ptr = try self.resolveInst(extra.lhs);
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src_ptr.freezeIfRegister(&self.register_manager);
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defer src_ptr.unfreezeIfRegister(&self.register_manager);
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const len = try self.resolveInst(extra.rhs);
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len.freezeIfRegister(&self.register_manager);
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defer len.unfreezeIfRegister(&self.register_manager);
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log.warn("dst_ptr = {}, src_ptr = {}, len = {}", .{ dst_ptr, src_ptr, len });
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try self.genInlineMemcpy(dst_ptr, src_ptr, len, .{});
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return self.finishAir(inst, .none, .{ pl_op.operand, .none, .none });
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}
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fn airTagName(self: *Self, inst: Air.Inst.Index) !void {
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