mirror of
https://github.com/ziglang/zig.git
synced 2026-01-22 07:15:25 +00:00
stage2 ARM: implement return types with abi size > 4
This commit is contained in:
joachimschmidt557
Jakub Konka
parent
ec54ceee6d
commit
ca97caab8a
@ -387,6 +387,18 @@ fn gen(self: *Self) !void {
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// sub sp, sp, #reloc
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const sub_reloc = try self.addNop();
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if (self.ret_mcv == .stack_offset) {
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// The address of where to store the return value is in
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// r0. As this register might get overwritten along the
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// way, save the address to the stack.
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const stack_offset = mem.alignForwardGeneric(u32, self.next_stack_offset, 4);
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self.next_stack_offset = stack_offset + 4;
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self.max_end_stack = @maximum(self.max_end_stack, self.next_stack_offset);
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try self.genSetStack(Type.usize, stack_offset, MCValue{ .register = .r0 });
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self.ret_mcv = MCValue{ .stack_offset = stack_offset };
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}
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_ = try self.addInst(.{
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.tag = .dbg_prologue_end,
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.cond = undefined,
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@ -1014,6 +1026,7 @@ fn airNot(self: *Self, inst: Air.Inst.Index) !void {
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break :result MCValue{ .register = dest_reg };
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},
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.Vector => return self.fail("TODO bitwise not for vectors", .{}),
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.Int => {
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const int_info = operand_ty.intInfo(self.target.*);
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if (int_info.bits <= 32) {
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@ -1666,6 +1679,8 @@ fn airLoad(self: *Self, inst: Air.Inst.Index) !void {
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}
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fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type) InnerError!void {
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const elem_size = @intCast(u32, value_ty.abiSize(self.target.*));
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switch (ptr) {
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.none => unreachable,
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.undef => unreachable,
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@ -1702,7 +1717,30 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type
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try self.genSetReg(value_ty, tmp_reg, value);
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try self.store(ptr, .{ .register = tmp_reg }, ptr_ty, value_ty);
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} else {
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return self.fail("TODO implement memcpy", .{});
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const regs = try self.register_manager.allocRegs(4, .{ null, null, null, null });
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self.register_manager.freezeRegs(®s);
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defer self.register_manager.unfreezeRegs(®s);
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const src_reg = regs[0];
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const dst_reg = addr_reg;
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const len_reg = regs[1];
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const count_reg = regs[2];
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const tmp_reg = regs[3];
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switch (value) {
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.stack_offset => |off| {
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// sub src_reg, fp, #off
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try self.genSetReg(ptr_ty, dst_reg, .{ .ptr_stack_offset = off });
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},
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.memory => |addr| try self.genSetReg(Type.usize, src_reg, .{ .immediate = @intCast(u32, addr) }),
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else => return self.fail("TODO store {} to register", .{value}),
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}
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// mov len, #elem_size
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try self.genSetReg(Type.usize, len_reg, .{ .immediate = elem_size });
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// memcpy(src, dst, len)
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try self.genInlineMemcpy(src_reg, dst_reg, len_reg, count_reg, tmp_reg);
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}
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},
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}
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@ -2408,9 +2446,7 @@ fn airArg(self: *Self, inst: Air.Inst.Index) !void {
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const mcv = switch (result) {
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// Copy registers to the stack
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.register => |reg| blk: {
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const abi_size = math.cast(u32, ty.abiSize(self.target.*)) catch {
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return self.fail("type '{}' too big to fit into stack frame", .{ty});
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};
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const abi_size = @intCast(u32, ty.abiSize(self.target.*));
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const abi_align = ty.abiAlignment(self.target.*);
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const stack_offset = try self.allocMem(inst, abi_size, abi_align);
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try self.genSetStack(ty, stack_offset, MCValue{ .register = reg });
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@ -2491,95 +2527,113 @@ fn airCall(self: *Self, inst: Air.Inst.Index) !void {
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// saving compare flags may require a new caller-saved register
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try self.spillCompareFlagsIfOccupied();
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if (info.return_value == .stack_offset) {
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const ret_ty = fn_ty.fnReturnType();
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const ret_abi_size = @intCast(u32, ret_ty.abiSize(self.target.*));
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const ret_abi_align = @intCast(u32, ret_ty.abiAlignment(self.target.*));
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const stack_offset = try self.allocMem(inst, ret_abi_size, ret_abi_align);
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var ptr_ty_payload: Type.Payload.ElemType = .{
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.base = .{ .tag = .single_mut_pointer },
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.data = ret_ty,
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};
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const ptr_ty = Type.initPayload(&ptr_ty_payload.base);
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try self.register_manager.getReg(.r0, inst);
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try self.genSetReg(ptr_ty, .r0, .{ .ptr_stack_offset = stack_offset });
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info.return_value = .{ .stack_offset = stack_offset };
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}
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// Make space for the arguments passed via the stack
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self.max_end_stack += info.stack_byte_count;
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for (info.args) |mc_arg, arg_i| {
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const arg = args[arg_i];
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const arg_ty = self.air.typeOf(arg);
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const arg_mcv = try self.resolveInst(args[arg_i]);
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switch (mc_arg) {
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.none => continue,
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.undef => unreachable,
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.immediate => unreachable,
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.unreach => unreachable,
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.dead => unreachable,
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.embedded_in_code => unreachable,
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.memory => unreachable,
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.compare_flags_signed => unreachable,
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.compare_flags_unsigned => unreachable,
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.ptr_stack_offset => unreachable,
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.ptr_embedded_in_code => unreachable,
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.register => |reg| {
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try self.register_manager.getReg(reg, null);
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try self.genSetReg(arg_ty, reg, arg_mcv);
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},
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.stack_offset => unreachable,
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.stack_argument_offset => |offset| try self.genSetStackArgument(
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arg_ty,
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info.stack_byte_count - offset,
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arg_mcv,
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),
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}
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}
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// Due to incremental compilation, how function calls are generated depends
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// on linking.
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if (self.bin_file.tag == link.File.Elf.base_tag or self.bin_file.tag == link.File.Coff.base_tag) {
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for (info.args) |mc_arg, arg_i| {
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const arg = args[arg_i];
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const arg_ty = self.air.typeOf(arg);
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const arg_mcv = try self.resolveInst(args[arg_i]);
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switch (self.bin_file.tag) {
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.elf, .coff => {
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if (self.air.value(callee)) |func_value| {
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if (func_value.castTag(.function)) |func_payload| {
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const func = func_payload.data;
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const ptr_bits = self.target.cpu.arch.ptrBitWidth();
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const ptr_bytes: u64 = @divExact(ptr_bits, 8);
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const got_addr = if (self.bin_file.cast(link.File.Elf)) |elf_file| blk: {
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const got = &elf_file.program_headers.items[elf_file.phdr_got_index.?];
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break :blk @intCast(u32, got.p_vaddr + func.owner_decl.link.elf.offset_table_index * ptr_bytes);
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} else if (self.bin_file.cast(link.File.Coff)) |coff_file|
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coff_file.offset_table_virtual_address + func.owner_decl.link.coff.offset_table_index * ptr_bytes
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else
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unreachable;
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switch (mc_arg) {
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.none => continue,
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.undef => unreachable,
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.immediate => unreachable,
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.unreach => unreachable,
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.dead => unreachable,
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.embedded_in_code => unreachable,
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.memory => unreachable,
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.compare_flags_signed => unreachable,
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.compare_flags_unsigned => unreachable,
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.ptr_stack_offset => unreachable,
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.ptr_embedded_in_code => unreachable,
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.register => |reg| {
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try self.register_manager.getReg(reg, null);
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try self.genSetReg(arg_ty, reg, arg_mcv);
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},
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.stack_offset => unreachable,
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.stack_argument_offset => |offset| try self.genSetStackArgument(
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arg_ty,
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info.stack_byte_count - offset,
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arg_mcv,
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),
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}
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}
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if (self.air.value(callee)) |func_value| {
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if (func_value.castTag(.function)) |func_payload| {
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const func = func_payload.data;
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const ptr_bits = self.target.cpu.arch.ptrBitWidth();
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const ptr_bytes: u64 = @divExact(ptr_bits, 8);
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const got_addr = if (self.bin_file.cast(link.File.Elf)) |elf_file| blk: {
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const got = &elf_file.program_headers.items[elf_file.phdr_got_index.?];
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break :blk @intCast(u32, got.p_vaddr + func.owner_decl.link.elf.offset_table_index * ptr_bytes);
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} else if (self.bin_file.cast(link.File.Coff)) |coff_file|
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coff_file.offset_table_virtual_address + func.owner_decl.link.coff.offset_table_index * ptr_bytes
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else
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unreachable;
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try self.genSetReg(Type.initTag(.usize), .lr, .{ .memory = got_addr });
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} else if (func_value.castTag(.extern_fn)) |_| {
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return self.fail("TODO implement calling extern functions", .{});
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try self.genSetReg(Type.initTag(.usize), .lr, .{ .memory = got_addr });
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} else if (func_value.castTag(.extern_fn)) |_| {
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return self.fail("TODO implement calling extern functions", .{});
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} else {
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return self.fail("TODO implement calling bitcasted functions", .{});
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}
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} else {
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return self.fail("TODO implement calling bitcasted functions", .{});
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assert(ty.zigTypeTag() == .Pointer);
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const mcv = try self.resolveInst(callee);
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try self.genSetReg(Type.initTag(.usize), .lr, mcv);
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}
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} else {
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assert(ty.zigTypeTag() == .Pointer);
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const mcv = try self.resolveInst(callee);
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try self.genSetReg(Type.initTag(.usize), .lr, mcv);
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}
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// TODO: add Instruction.supportedOn
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// function for ARM
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if (Target.arm.featureSetHas(self.target.cpu.features, .has_v5t)) {
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_ = try self.addInst(.{
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.tag = .blx,
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.data = .{ .reg = .lr },
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});
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} else {
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return self.fail("TODO fix blx emulation for ARM <v5", .{});
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// _ = try self.addInst(.{
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// .tag = .mov,
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// .data = .{ .rr_op = .{
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// .rd = .lr,
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// .rn = .r0,
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// .op = Instruction.Operand.reg(.pc, Instruction.Operand.Shift.none),
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// } },
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// });
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// _ = try self.addInst(.{
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// .tag = .bx,
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// .data = .{ .reg = .lr },
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// });
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}
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} else if (self.bin_file.cast(link.File.MachO)) |_| {
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unreachable; // unsupported architecture for MachO
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} else if (self.bin_file.cast(link.File.Plan9)) |_| {
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return self.fail("TODO implement call on plan9 for {}", .{self.target.cpu.arch});
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} else unreachable;
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// TODO: add Instruction.supportedOn
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// function for ARM
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if (Target.arm.featureSetHas(self.target.cpu.features, .has_v5t)) {
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_ = try self.addInst(.{
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.tag = .blx,
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.data = .{ .reg = .lr },
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});
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} else {
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return self.fail("TODO fix blx emulation for ARM <v5", .{});
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// _ = try self.addInst(.{
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// .tag = .mov,
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// .data = .{ .rr_op = .{
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// .rd = .lr,
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// .rn = .r0,
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// .op = Instruction.Operand.reg(.pc, Instruction.Operand.Shift.none),
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// } },
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// });
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// _ = try self.addInst(.{
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// .tag = .bx,
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// .data = .{ .reg = .lr },
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// });
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}
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},
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.macho => unreachable, // unsupported architecture for MachO
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.plan9 => return self.fail("TODO implement call on plan9 for {}", .{self.target.cpu.arch}),
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else => unreachable,
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}
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const result: MCValue = result: {
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switch (info.return_value) {
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@ -2610,7 +2664,26 @@ fn airCall(self: *Self, inst: Air.Inst.Index) !void {
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fn ret(self: *Self, mcv: MCValue) !void {
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const ret_ty = self.fn_type.fnReturnType();
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try self.setRegOrMem(ret_ty, self.ret_mcv, mcv);
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switch (self.ret_mcv) {
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.none => {},
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.register => |reg| {
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// Return result by value
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try self.genSetReg(ret_ty, reg, mcv);
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},
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.stack_offset => {
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// Return result by reference
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//
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// self.ret_mcv is an address to where this function
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// should store its result into
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var ptr_ty_payload: Type.Payload.ElemType = .{
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.base = .{ .tag = .single_mut_pointer },
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.data = ret_ty,
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};
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const ptr_ty = Type.initPayload(&ptr_ty_payload.base);
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try self.store(self.ret_mcv, mcv, ptr_ty, ret_ty);
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},
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else => unreachable, // invalid return result
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}
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// Just add space for an instruction, patch this later
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try self.exitlude_jump_relocs.append(self.gpa, try self.addNop());
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@ -3524,9 +3597,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
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});
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},
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.immediate => |x| {
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if (x > math.maxInt(u32)) return self.fail("ARM registers are 32-bit wide", .{});
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if (Instruction.Operand.fromU32(@intCast(u32, x))) |op| {
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if (Instruction.Operand.fromU32(x)) |op| {
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_ = try self.addInst(.{
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.tag = .mov,
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.data = .{ .rr_op = .{
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@ -3535,7 +3606,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
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.op = op,
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} },
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});
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} else if (Instruction.Operand.fromU32(~@intCast(u32, x))) |op| {
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} else if (Instruction.Operand.fromU32(~x)) |op| {
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_ = try self.addInst(.{
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.tag = .mvn,
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.data = .{ .rr_op = .{
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@ -4262,6 +4333,25 @@ fn resolveCallingConventionValues(self: *Self, fn_ty: Type) !CallMCValues {
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var ncrn: usize = 0; // Next Core Register Number
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var nsaa: u32 = 0; // Next stacked argument address
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if (ret_ty.zigTypeTag() == .NoReturn) {
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result.return_value = .{ .unreach = {} };
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} else if (!ret_ty.hasRuntimeBits()) {
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result.return_value = .{ .none = {} };
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} else {
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const ret_ty_size = @intCast(u32, ret_ty.abiSize(self.target.*));
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// TODO handle cases where multiple registers are used
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if (ret_ty_size <= 4) {
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result.return_value = .{ .register = c_abi_int_return_regs[0] };
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} else {
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// The result is returned by reference, not by
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// value. This means that r0 will contain the
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// address of where this function should write the
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// result into.
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result.return_value = .{ .stack_offset = 0 };
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ncrn = 1;
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}
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}
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for (param_types) |ty, i| {
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if (ty.abiAlignment(self.target.*) == 8)
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ncrn = std.mem.alignForwardGeneric(usize, ncrn, 2);
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@ -4290,6 +4380,23 @@ fn resolveCallingConventionValues(self: *Self, fn_ty: Type) !CallMCValues {
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result.stack_align = 8;
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},
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.Unspecified => {
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if (ret_ty.zigTypeTag() == .NoReturn) {
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result.return_value = .{ .unreach = {} };
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} else if (!ret_ty.hasRuntimeBits()) {
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result.return_value = .{ .none = {} };
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} else {
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const ret_ty_size = @intCast(u32, ret_ty.abiSize(self.target.*));
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if (ret_ty_size <= 4) {
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result.return_value = .{ .register = .r0 };
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} else {
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// The result is returned by reference, not by
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// value. This means that r0 will contain the
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// address of where this function should write the
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// result into.
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result.return_value = .{ .stack_offset = 0 };
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}
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}
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var stack_offset: u32 = 0;
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for (param_types) |ty, i| {
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@ -4308,22 +4415,6 @@ fn resolveCallingConventionValues(self: *Self, fn_ty: Type) !CallMCValues {
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else => return self.fail("TODO implement function parameters for {} on arm", .{cc}),
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}
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if (ret_ty.zigTypeTag() == .NoReturn) {
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result.return_value = .{ .unreach = {} };
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} else if (!ret_ty.hasRuntimeBits()) {
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result.return_value = .{ .none = {} };
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} else switch (cc) {
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.Naked => unreachable,
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.Unspecified, .C => {
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const ret_ty_size = @intCast(u32, ret_ty.abiSize(self.target.*));
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if (ret_ty_size <= 4) {
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result.return_value = .{ .register = c_abi_int_return_regs[0] };
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} else {
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return self.fail("TODO support more return types for ARM backend", .{});
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}
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},
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else => return self.fail("TODO implement function return values for {}", .{cc}),
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}
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return result;
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}
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@ -113,7 +113,6 @@ fn first4KeysOfHomeRow() []const u8 {
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test "return string from function" {
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
|
||||
|
||||
try expect(mem.eql(u8, first4KeysOfHomeRow(), "aoeu"));
|
||||
}
|
||||
|
||||
@ -381,7 +381,6 @@ test "align 1 field before self referential align 8 field as slice return type"
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
|
||||
|
||||
const result = alloc(Expr);
|
||||
try expect(result.len == 0);
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user