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Update changes due to different CPU feature sets

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llvm commit b2851aea80e5a8f0cfd6c3c5a56a6b00fb28c6b6
This commit is contained in:
Jakub Konka 2020-12-16 18:25:25 +01:00
parent 1c40a4df09
commit 4b62f1bd93
3 changed files with 9 additions and 8 deletions
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10
lib/std/target.zig
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@ -551,7 +551,7 @@ pub const Target = struct {
pub const Set = struct {
ints: [usize_count]usize,
pub const needed_bit_count = 168;
pub const needed_bit_count = 192;
pub const byte_count = (needed_bit_count + 7) / 8;
pub const usize_count = (byte_count + (@sizeOf(usize) - 1)) / @sizeOf(usize);
pub const Index = std.math.Log2Int(std.meta.Int(.unsigned, usize_count * @bitSizeOf(usize)));
@ -828,7 +828,7 @@ pub const Target = struct {
.amdgcn => ._NONE,
.bpfel => ._BPF,
.bpfeb => ._BPF,
.csky => ._CSKY,
.csky => ._NONE,
.sparcv9 => ._SPARCV9,
.s390x => ._S390,
.ve => ._NONE,
@ -1149,9 +1149,9 @@ pub const Target = struct {
pub fn baseline(arch: Arch) *const Model {
return switch (arch) {
.arm, .armeb, .thumb, .thumbeb => &arm.cpu.baseline,
.riscv32 => &riscv.cpu.baseline_rv32,
.riscv64 => &riscv.cpu.baseline_rv64,
// .arm, .armeb, .thumb, .thumbeb => &arm.cpu.baseline, // TODO removed in LLVM 12
// .riscv32 => &riscv.cpu.baseline_rv32, // TODO removed in LLVM 12
// .riscv64 => &riscv.cpu.baseline_rv64, // TODO removed in LLVM 12
.i386 => &x86.cpu.pentium4,
.nvptx, .nvptx64 => &nvptx.cpu.sm_20,

6
src/codegen.zig
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@ -1689,7 +1689,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
// TODO: add Instruction.supportedOn
// function for ARM
if (Target.arm.featureSetHas(self.target.cpu.features, .has_v5t)) {
if (Target.arm.featureSetHas(self.target.cpu.features, .armv5t)) {
writeInt(u32, try self.code.addManyAsArray(4), Instruction.blx(.al, .lr).toU32());
} else {
writeInt(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, .lr, Instruction.Operand.reg(.pc, Instruction.Operand.Shift.none)).toU32());
@ -2625,7 +2625,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
} else if (Instruction.Operand.fromU32(~@intCast(u32, x))) |op| {
writeInt(u32, try self.code.addManyAsArray(4), Instruction.mvn(.al, reg, op).toU32());
} else if (x <= math.maxInt(u16)) {
if (Target.arm.featureSetHas(self.target.cpu.features, .has_v7)) {
if (Target.arm.featureSetHas(self.target.cpu.features, .armv7_a)) {
writeInt(u32, try self.code.addManyAsArray(4), Instruction.movw(.al, reg, @intCast(u16, x)).toU32());
} else {
writeInt(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, reg, Instruction.Operand.imm(@truncate(u8, x), 0)).toU32());
@ -2634,7 +2634,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
} else {
// TODO write constant to code and load
// relative to pc
if (Target.arm.featureSetHas(self.target.cpu.features, .has_v7)) {
if (Target.arm.featureSetHas(self.target.cpu.features, .armv7_a)) {
// immediate: 0xaaaabbbb
// movw reg, #0xbbbb
// movt reg, #0xaaaa

1
src/target.zig
View File

@ -240,6 +240,7 @@ pub fn archToLLVM(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {
.avr => .avr,
.bpfel => .bpfel,
.bpfeb => .bpfeb,
.csky => .csky,
.hexagon => .hexagon,
.mips => .mips,
.mipsel => .mipsel,