From 4b62f1bd93abfa2ae5aec2240bfac9327035901b Mon Sep 17 00:00:00 2001
From: Jakub Konka <kubkon@jakubkonka.com>
Date: Wed, 16 Dec 2020 18:25:25 +0100
Subject: [PATCH] Update changes due to different CPU feature sets

llvm commit b2851aea80e5a8f0cfd6c3c5a56a6b00fb28c6b6
---
 lib/std/target.zig | 10 +++++-----
 src/codegen.zig    |  6 +++---
 src/target.zig     |  1 +
 3 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/lib/std/target.zig b/lib/std/target.zig
index 287d945036..ef07f356b3 100644
--- a/lib/std/target.zig
+++ b/lib/std/target.zig
@@ -551,7 +551,7 @@ pub const Target = struct {
             pub const Set = struct {
                 ints: [usize_count]usize,
 
-                pub const needed_bit_count = 168;
+                pub const needed_bit_count = 192;
                 pub const byte_count = (needed_bit_count + 7) / 8;
                 pub const usize_count = (byte_count + (@sizeOf(usize) - 1)) / @sizeOf(usize);
                 pub const Index = std.math.Log2Int(std.meta.Int(.unsigned, usize_count * @bitSizeOf(usize)));
@@ -828,7 +828,7 @@ pub const Target = struct {
                     .amdgcn => ._NONE,
                     .bpfel => ._BPF,
                     .bpfeb => ._BPF,
-                    .csky => ._CSKY,
+                    .csky => ._NONE,
                     .sparcv9 => ._SPARCV9,
                     .s390x => ._S390,
                     .ve => ._NONE,
@@ -1149,9 +1149,9 @@ pub const Target = struct {
 
             pub fn baseline(arch: Arch) *const Model {
                 return switch (arch) {
-                    .arm, .armeb, .thumb, .thumbeb => &arm.cpu.baseline,
-                    .riscv32 => &riscv.cpu.baseline_rv32,
-                    .riscv64 => &riscv.cpu.baseline_rv64,
+                    // .arm, .armeb, .thumb, .thumbeb => &arm.cpu.baseline, // TODO removed in LLVM 12
+                    // .riscv32 => &riscv.cpu.baseline_rv32, // TODO removed in LLVM 12
+                    // .riscv64 => &riscv.cpu.baseline_rv64, // TODO removed in LLVM 12
                     .i386 => &x86.cpu.pentium4,
                     .nvptx, .nvptx64 => &nvptx.cpu.sm_20,
 
diff --git a/src/codegen.zig b/src/codegen.zig
index 3b0a383a71..f982dbf382 100644
--- a/src/codegen.zig
+++ b/src/codegen.zig
@@ -1689,7 +1689,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
 
                                 // TODO: add Instruction.supportedOn
                                 // function for ARM
-                                if (Target.arm.featureSetHas(self.target.cpu.features, .has_v5t)) {
+                                if (Target.arm.featureSetHas(self.target.cpu.features, .armv5t)) {
                                     writeInt(u32, try self.code.addManyAsArray(4), Instruction.blx(.al, .lr).toU32());
                                 } else {
                                     writeInt(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, .lr, Instruction.Operand.reg(.pc, Instruction.Operand.Shift.none)).toU32());
@@ -2625,7 +2625,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
                         } else if (Instruction.Operand.fromU32(~@intCast(u32, x))) |op| {
                             writeInt(u32, try self.code.addManyAsArray(4), Instruction.mvn(.al, reg, op).toU32());
                         } else if (x <= math.maxInt(u16)) {
-                            if (Target.arm.featureSetHas(self.target.cpu.features, .has_v7)) {
+                            if (Target.arm.featureSetHas(self.target.cpu.features, .armv7_a)) {
                                 writeInt(u32, try self.code.addManyAsArray(4), Instruction.movw(.al, reg, @intCast(u16, x)).toU32());
                             } else {
                                 writeInt(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, reg, Instruction.Operand.imm(@truncate(u8, x), 0)).toU32());
@@ -2634,7 +2634,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
                         } else {
                             // TODO write constant to code and load
                             // relative to pc
-                            if (Target.arm.featureSetHas(self.target.cpu.features, .has_v7)) {
+                            if (Target.arm.featureSetHas(self.target.cpu.features, .armv7_a)) {
                                 // immediate: 0xaaaabbbb
                                 // movw reg, #0xbbbb
                                 // movt reg, #0xaaaa
diff --git a/src/target.zig b/src/target.zig
index bd48a218d5..d4e85c1cf6 100644
--- a/src/target.zig
+++ b/src/target.zig
@@ -240,6 +240,7 @@ pub fn archToLLVM(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {
         .avr => .avr,
         .bpfel => .bpfel,
         .bpfeb => .bpfeb,
+        .csky => .csky,
         .hexagon => .hexagon,
         .mips => .mips,
         .mipsel => .mipsel,