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Merge pull request #6097 from joachimschmidt557/stage2-arm
Start working on stage2 ARM backend
This commit is contained in:
Andrew Kelley
GitHub
commit
385786eedc
@ -76,8 +76,8 @@ pub fn generateSymbol(
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switch (bin_file.options.target.cpu.arch) {
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.wasm32 => unreachable, // has its own code path
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.wasm64 => unreachable, // has its own code path
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//.arm => return Function(.arm).generateSymbol(bin_file, src, typed_value, code, dbg_line, dbg_info, dbg_info_type_relocs),
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//.armeb => return Function(.armeb).generateSymbol(bin_file, src, typed_value, code, dbg_line, dbg_info, dbg_info_type_relocs),
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.arm => return Function(.arm).generateSymbol(bin_file, src, typed_value, code, dbg_line, dbg_info, dbg_info_type_relocs),
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.armeb => return Function(.armeb).generateSymbol(bin_file, src, typed_value, code, dbg_line, dbg_info, dbg_info_type_relocs),
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//.aarch64 => return Function(.aarch64).generateSymbol(bin_file, src, typed_value, code, dbg_line, dbg_info, dbg_info_type_relocs),
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//.aarch64_be => return Function(.aarch64_be).generateSymbol(bin_file, src, typed_value, code, dbg_line, dbg_info, dbg_info_type_relocs),
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//.aarch64_32 => return Function(.aarch64_32).generateSymbol(bin_file, src, typed_value, code, dbg_line, dbg_info, dbg_info_type_relocs),
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@ -1270,6 +1270,12 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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var instr = Instruction{ .condition = .always, .input0 = .zero, .input1 = .zero, .modify_flags = false, .output = .discard, .command = .undefined1 };
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mem.writeIntLittle(u16, self.code.items[self.code.items.len - 2 ..][0..2], @bitCast(u16, instr));
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},
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.arm => {
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.bkpt(0).toU32());
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},
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.armeb => {
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mem.writeIntBig(u32, try self.code.addManyAsArray(4), Instruction.bkpt(0).toU32());
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},
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else => return self.fail(src, "TODO implement @breakpoint() for {}", .{self.target.cpu.arch}),
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}
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return .none;
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@ -1393,6 +1399,31 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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return self.fail(inst.base.src, "TODO implement calling runtime known function pointer", .{});
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}
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},
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.arm => {
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if (info.args.len > 0) return self.fail(inst.base.src, "TODO implement fn args for {}", .{self.target.cpu.arch});
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if (inst.func.cast(ir.Inst.Constant)) |func_inst| {
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if (func_inst.val.cast(Value.Payload.Function)) |func_val| {
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const func = func_val.func;
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const got = &elf_file.program_headers.items[elf_file.phdr_got_index.?];
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const ptr_bits = self.target.cpu.arch.ptrBitWidth();
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const ptr_bytes: u64 = @divExact(ptr_bits, 8);
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const got_addr = @intCast(u32, got.p_vaddr + func.owner_decl.link.elf.offset_table_index * ptr_bytes);
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// TODO only works with leaf functions
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// at the moment, which works fine for
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// Hello World, but not for real code
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// of course. Add pushing lr to stack
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// and popping after call
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try self.genSetReg(inst.base.src, .lr, .{ .memory = got_addr });
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.blx(.al, .lr).toU32());
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} else {
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return self.fail(inst.base.src, "TODO implement calling bitcasted functions", .{});
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}
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} else {
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return self.fail(inst.base.src, "TODO implement calling runtime known function pointer", .{});
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}
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},
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else => return self.fail(inst.base.src, "TODO implement call for {}", .{self.target.cpu.arch}),
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}
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} else if (self.bin_file.cast(link.File.MachO)) |macho_file| {
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@ -1449,6 +1480,9 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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.riscv64 => {
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.jalr(.zero, 0, .ra).toU32());
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},
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.arm => {
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.bx(.al, .lr).toU32());
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},
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else => return self.fail(src, "TODO implement return for {}", .{self.target.cpu.arch}),
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}
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return .unreach;
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@ -1699,6 +1733,36 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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return self.fail(inst.base.src, "TODO implement support for more SPU II assembly instructions", .{});
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}
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},
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.arm => {
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for (inst.inputs) |input, i| {
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if (input.len < 3 or input[0] != '{' or input[input.len - 1] != '}') {
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return self.fail(inst.base.src, "unrecognized asm input constraint: '{}'", .{input});
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}
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const reg_name = input[1 .. input.len - 1];
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const reg = parseRegName(reg_name) orelse
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return self.fail(inst.base.src, "unrecognized register: '{}'", .{reg_name});
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const arg = try self.resolveInst(inst.args[i]);
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try self.genSetReg(inst.base.src, reg, arg);
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}
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if (mem.eql(u8, inst.asm_source, "svc #0")) {
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.svc(.al, 0).toU32());
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} else {
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return self.fail(inst.base.src, "TODO implement support for more arm assembly instructions", .{});
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}
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if (inst.output) |output| {
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if (output.len < 4 or output[0] != '=' or output[1] != '{' or output[output.len - 1] != '}') {
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return self.fail(inst.base.src, "unrecognized asm output constraint: '{}'", .{output});
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}
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const reg_name = output[2 .. output.len - 1];
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const reg = parseRegName(reg_name) orelse
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return self.fail(inst.base.src, "unrecognized register: '{}'", .{reg_name});
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return MCValue{ .register = reg };
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} else {
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return MCValue.none;
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}
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},
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.riscv64 => {
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for (inst.inputs) |input, i| {
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if (input.len < 3 or input[0] != '{' or input[input.len - 1] != '}') {
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@ -1892,6 +1956,58 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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fn genSetReg(self: *Self, src: usize, reg: Register, mcv: MCValue) InnerError!void {
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switch (arch) {
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.arm => switch (mcv) {
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.dead => unreachable,
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.ptr_stack_offset => unreachable,
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.ptr_embedded_in_code => unreachable,
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.unreach, .none => return, // Nothing to do.
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.undef => {
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if (!self.wantSafety())
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return; // The already existing value will do just fine.
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// Write the debug undefined value.
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return self.genSetReg(src, reg, .{ .immediate = 0xaaaaaaaa });
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},
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.immediate => |x| {
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// TODO better analysis of x to determine the
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// least amount of necessary instructions (use
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// more intelligent rotating)
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if (x <= math.maxInt(u8)) {
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, 0, reg, Instruction.Operand.imm(@truncate(u8, x), 0)).toU32());
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return;
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} else if (x <= math.maxInt(u16)) {
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// TODO Use movw Note: Not supported on
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// all ARM targets!
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, 0, reg, Instruction.Operand.imm(@truncate(u8, x), 0)).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, 0, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 8), 12)).toU32());
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} else if (x <= math.maxInt(u32)) {
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// TODO Use movw and movt Note: Not
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// supported on all ARM targets! Also TODO
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// write constant to code and load
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// relative to pc
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// immediate: 0xaabbccdd
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// mov reg, #0xaa
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// orr reg, reg, #0xbb, 24
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// orr reg, reg, #0xcc, 16
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// orr reg, reg, #0xdd, 8
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, 0, reg, Instruction.Operand.imm(@truncate(u8, x), 0)).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, 0, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 8), 12)).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, 0, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 16), 8)).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, 0, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 24), 4)).toU32());
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return;
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} else {
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return self.fail(src, "ARM registers are 32-bit wide", .{});
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}
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},
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.memory => |addr| {
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// The value is in memory at a hard-coded address.
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// If the type is a pointer, it means the pointer address is at this memory location.
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try self.genSetReg(src, reg, .{ .immediate = addr });
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.ldr(.al, reg, reg, Instruction.Offset.none).toU32());
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},
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else => return self.fail(src, "TODO implement getSetReg for arm {}", .{mcv}),
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},
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.riscv64 => switch (mcv) {
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.dead => unreachable,
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.ptr_stack_offset => unreachable,
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@ -2372,6 +2488,8 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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.x86_64 => @import("codegen/x86_64.zig"),
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.riscv64 => @import("codegen/riscv64.zig"),
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.spu_2 => @import("codegen/spu-mk2.zig"),
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.arm => @import("codegen/arm.zig"),
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.armeb => @import("codegen/arm.zig"),
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else => struct {
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pub const Register = enum {
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dummy,
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607
src-self-hosted/codegen/arm.zig
Normal file
607
src-self-hosted/codegen/arm.zig
Normal file
@ -0,0 +1,607 @@
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const std = @import("std");
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const DW = std.dwarf;
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const testing = std.testing;
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/// The condition field specifies the flags neccessary for an
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/// Instruction to be executed
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pub const Condition = enum(u4) {
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/// equal
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eq,
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/// not equal
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ne,
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/// unsigned higher or same
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cs,
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/// unsigned lower
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cc,
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/// negative
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mi,
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/// positive or zero
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pl,
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/// overflow
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vs,
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/// no overflow
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vc,
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/// unsigned higer
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hi,
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/// unsigned lower or same
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ls,
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/// greater or equal
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ge,
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/// less than
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lt,
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/// greater than
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gt,
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/// less than or equal
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le,
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/// always
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al,
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};
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/// Represents a register in the ARM instruction set architecture
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pub const Register = enum(u5) {
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r0,
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r1,
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r2,
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r3,
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r4,
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r5,
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r6,
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r7,
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r8,
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r9,
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r10,
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r11,
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r12,
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r13,
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r14,
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r15,
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/// Argument / result / scratch register 1
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a1,
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/// Argument / result / scratch register 2
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a2,
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/// Argument / scratch register 3
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a3,
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/// Argument / scratch register 4
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a4,
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/// Variable-register 1
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v1,
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/// Variable-register 2
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v2,
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/// Variable-register 3
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v3,
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/// Variable-register 4
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v4,
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/// Variable-register 5
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v5,
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/// Platform register
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v6,
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/// Variable-register 7
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v7,
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/// Frame pointer or Variable-register 8
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fp,
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/// Intra-Procedure-call scratch register
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ip,
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/// Stack pointer
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sp,
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/// Link register
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lr,
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/// Program counter
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pc,
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/// Returns the unique 4-bit ID of this register which is used in
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/// the machine code
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pub fn id(self: Register) u4 {
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return @truncate(u4, @enumToInt(self));
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}
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/// Returns the index into `callee_preserved_regs`.
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pub fn allocIndex(self: Register) ?u4 {
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inline for (callee_preserved_regs) |cpreg, i| {
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if (self.id() == cpreg.id()) return i;
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}
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return null;
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}
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pub fn dwarfLocOp(self: Register) u8 {
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return @as(u8, self.id()) + DW.OP_reg0;
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}
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};
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test "Register.id" {
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testing.expectEqual(@as(u4, 15), Register.r15.id());
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testing.expectEqual(@as(u4, 15), Register.pc.id());
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}
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pub const callee_preserved_regs = [_]Register{ .r0, .r1, .r2, .r3, .r4, .r5, .r6, .r7, .r8, .r10 };
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pub const c_abi_int_param_regs = [_]Register{ .r0, .r1, .r2, .r3 };
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pub const c_abi_int_return_regs = [_]Register{ .r0, .r1 };
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/// Represents an instruction in the ARM instruction set architecture
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pub const Instruction = union(enum) {
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DataProcessing: packed struct {
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// Note to self: The order of the fields top-to-bottom is
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// right-to-left in the actual 32-bit int representation
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op2: u12,
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rd: u4,
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rn: u4,
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s: u1,
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opcode: u4,
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i: u1,
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fixed: u2 = 0b00,
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cond: u4,
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},
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SingleDataTransfer: packed struct {
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offset: u12,
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rd: u4,
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rn: u4,
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l: u1,
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w: u1,
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b: u1,
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u: u1,
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p: u1,
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i: u1,
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fixed: u2 = 0b01,
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cond: u4,
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},
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Branch: packed struct {
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offset: u24,
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link: u1,
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fixed: u3 = 0b101,
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cond: u4,
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},
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BranchExchange: packed struct {
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rn: u4,
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fixed_1: u1 = 0b1,
|
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link: u1,
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fixed_2: u22 = 0b0001_0010_1111_1111_1111_00,
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cond: u4,
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},
|
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SupervisorCall: packed struct {
|
||||
comment: u24,
|
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fixed: u4 = 0b1111,
|
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cond: u4,
|
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},
|
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Breakpoint: packed struct {
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imm4: u4,
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fixed_1: u4 = 0b0111,
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imm12: u12,
|
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fixed_2_and_cond: u12 = 0b1110_0001_0010,
|
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},
|
||||
|
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/// Represents the possible operations which can be performed by a
|
||||
/// DataProcessing instruction
|
||||
const Opcode = enum(u4) {
|
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// Rd := Op1 AND Op2
|
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@"and",
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// Rd := Op1 EOR Op2
|
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eor,
|
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// Rd := Op1 - Op2
|
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sub,
|
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// Rd := Op2 - Op1
|
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rsb,
|
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// Rd := Op1 + Op2
|
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add,
|
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// Rd := Op1 + Op2 + C
|
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adc,
|
||||
// Rd := Op1 - Op2 + C - 1
|
||||
sbc,
|
||||
// Rd := Op2 - Op1 + C - 1
|
||||
rsc,
|
||||
// set condition codes on Op1 AND Op2
|
||||
tst,
|
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// set condition codes on Op1 EOR Op2
|
||||
teq,
|
||||
// set condition codes on Op1 - Op2
|
||||
cmp,
|
||||
// set condition codes on Op1 + Op2
|
||||
cmn,
|
||||
// Rd := Op1 OR Op2
|
||||
orr,
|
||||
// Rd := Op2
|
||||
mov,
|
||||
// Rd := Op1 AND NOT Op2
|
||||
bic,
|
||||
// Rd := NOT Op2
|
||||
mvn,
|
||||
};
|
||||
|
||||
/// Represents the second operand to a data processing instruction
|
||||
/// which can either be content from a register or an immediate
|
||||
/// value
|
||||
pub const Operand = union(enum) {
|
||||
Register: packed struct {
|
||||
rm: u4,
|
||||
shift: u8,
|
||||
},
|
||||
Immediate: packed struct {
|
||||
imm: u8,
|
||||
rotate: u4,
|
||||
},
|
||||
|
||||
/// Represents multiple ways a register can be shifted. A
|
||||
/// register can be shifted by a specific immediate value or
|
||||
/// by the contents of another register
|
||||
pub const Shift = union(enum) {
|
||||
Immediate: packed struct {
|
||||
fixed: u1 = 0b0,
|
||||
typ: u2,
|
||||
amount: u5,
|
||||
},
|
||||
Register: packed struct {
|
||||
fixed_1: u1 = 0b1,
|
||||
typ: u2,
|
||||
fixed_2: u1 = 0b0,
|
||||
rs: u4,
|
||||
},
|
||||
|
||||
const Type = enum(u2) {
|
||||
LogicalLeft,
|
||||
LogicalRight,
|
||||
ArithmeticRight,
|
||||
RotateRight,
|
||||
};
|
||||
|
||||
const none = Shift{
|
||||
.Immediate = .{
|
||||
.amount = 0,
|
||||
.typ = 0,
|
||||
},
|
||||
};
|
||||
|
||||
pub fn toU8(self: Shift) u8 {
|
||||
return switch (self) {
|
||||
.Register => |v| @bitCast(u8, v),
|
||||
.Immediate => |v| @bitCast(u8, v),
|
||||
};
|
||||
}
|
||||
|
||||
pub fn reg(rs: Register, typ: Type) Shift {
|
||||
return Shift{
|
||||
.Register = .{
|
||||
.rs = rs.id(),
|
||||
.typ = @enumToInt(typ),
|
||||
},
|
||||
};
|
||||
}
|
||||
|
||||
pub fn imm(amount: u5, typ: Type) Shift {
|
||||
return Shift{
|
||||
.Immediate = .{
|
||||
.amount = amount,
|
||||
.typ = @enumToInt(typ),
|
||||
},
|
||||
};
|
||||
}
|
||||
};
|
||||
|
||||
pub fn toU12(self: Operand) u12 {
|
||||
return switch (self) {
|
||||
.Register => |v| @bitCast(u12, v),
|
||||
.Immediate => |v| @bitCast(u12, v),
|
||||
};
|
||||
}
|
||||
|
||||
pub fn reg(rm: Register, shift: Shift) Operand {
|
||||
return Operand{
|
||||
.Register = .{
|
||||
.rm = rm.id(),
|
||||
.shift = shift.toU8(),
|
||||
},
|
||||
};
|
||||
}
|
||||
|
||||
pub fn imm(immediate: u8, rotate: u4) Operand {
|
||||
return Operand{
|
||||
.Immediate = .{
|
||||
.imm = immediate,
|
||||
.rotate = rotate,
|
||||
},
|
||||
};
|
||||
}
|
||||
};
|
||||
|
||||
/// Represents the offset operand of a load or store
|
||||
/// instruction. Data can be loaded from memory with either an
|
||||
/// immediate offset or an offset that is stored in some register.
|
||||
pub const Offset = union(enum) {
|
||||
Immediate: u12,
|
||||
Register: packed struct {
|
||||
rm: u4,
|
||||
shift: u8,
|
||||
},
|
||||
|
||||
pub const none = Offset{
|
||||
.Immediate = 0,
|
||||
};
|
||||
|
||||
pub fn toU12(self: Offset) u12 {
|
||||
return switch (self) {
|
||||
.Register => |v| @bitCast(u12, v),
|
||||
.Immediate => |v| v,
|
||||
};
|
||||
}
|
||||
|
||||
pub fn reg(rm: Register, shift: u8) Offset {
|
||||
return Offset{
|
||||
.Register = .{
|
||||
.rm = rm.id(),
|
||||
.shift = shift,
|
||||
},
|
||||
};
|
||||
}
|
||||
|
||||
pub fn imm(immediate: u8) Offset {
|
||||
return Offset{
|
||||
.Immediate = immediate,
|
||||
};
|
||||
}
|
||||
};
|
||||
|
||||
pub fn toU32(self: Instruction) u32 {
|
||||
return switch (self) {
|
||||
.DataProcessing => |v| @bitCast(u32, v),
|
||||
.SingleDataTransfer => |v| @bitCast(u32, v),
|
||||
.Branch => |v| @bitCast(u32, v),
|
||||
.BranchExchange => |v| @bitCast(u32, v),
|
||||
.SupervisorCall => |v| @bitCast(u32, v),
|
||||
.Breakpoint => |v| @intCast(u32, v.imm4) | (@intCast(u32, v.fixed_1) << 4) | (@intCast(u32, v.imm12) << 8) | (@intCast(u32, v.fixed_2_and_cond) << 20),
|
||||
};
|
||||
}
|
||||
|
||||
// Helper functions for the "real" functions below
|
||||
|
||||
fn dataProcessing(
|
||||
cond: Condition,
|
||||
opcode: Opcode,
|
||||
s: u1,
|
||||
rd: Register,
|
||||
rn: Register,
|
||||
op2: Operand,
|
||||
) Instruction {
|
||||
return Instruction{
|
||||
.DataProcessing = .{
|
||||
.cond = @enumToInt(cond),
|
||||
.i = if (op2 == .Immediate) 1 else 0,
|
||||
.opcode = @enumToInt(opcode),
|
||||
.s = s,
|
||||
.rn = rn.id(),
|
||||
.rd = rd.id(),
|
||||
.op2 = op2.toU12(),
|
||||
},
|
||||
};
|
||||
}
|
||||
|
||||
fn singleDataTransfer(
|
||||
cond: Condition,
|
||||
rd: Register,
|
||||
rn: Register,
|
||||
offset: Offset,
|
||||
pre_post: u1,
|
||||
up_down: u1,
|
||||
byte_word: u1,
|
||||
writeback: u1,
|
||||
load_store: u1,
|
||||
) Instruction {
|
||||
return Instruction{
|
||||
.SingleDataTransfer = .{
|
||||
.cond = @enumToInt(cond),
|
||||
.rn = rn.id(),
|
||||
.rd = rd.id(),
|
||||
.offset = offset.toU12(),
|
||||
.l = load_store,
|
||||
.w = writeback,
|
||||
.b = byte_word,
|
||||
.u = up_down,
|
||||
.p = pre_post,
|
||||
.i = if (offset == .Immediate) 0 else 1,
|
||||
},
|
||||
};
|
||||
}
|
||||
|
||||
fn branch(cond: Condition, offset: i24, link: u1) Instruction {
|
||||
return Instruction{
|
||||
.Branch = .{
|
||||
.cond = @enumToInt(cond),
|
||||
.link = link,
|
||||
.offset = @bitCast(u24, offset),
|
||||
},
|
||||
};
|
||||
}
|
||||
|
||||
fn branchExchange(cond: Condition, rn: Register, link: u1) Instruction {
|
||||
return Instruction{
|
||||
.BranchExchange = .{
|
||||
.cond = @enumToInt(cond),
|
||||
.link = link,
|
||||
.rn = rn.id(),
|
||||
},
|
||||
};
|
||||
}
|
||||
|
||||
fn supervisorCall(cond: Condition, comment: u24) Instruction {
|
||||
return Instruction{
|
||||
.SupervisorCall = .{
|
||||
.cond = @enumToInt(cond),
|
||||
.comment = comment,
|
||||
},
|
||||
};
|
||||
}
|
||||
|
||||
fn breakpoint(imm: u16) Instruction {
|
||||
return Instruction{
|
||||
.Breakpoint = .{
|
||||
.imm12 = @truncate(u12, imm >> 4),
|
||||
.imm4 = @truncate(u4, imm),
|
||||
},
|
||||
};
|
||||
}
|
||||
|
||||
// Public functions replicating assembler syntax as closely as
|
||||
// possible
|
||||
|
||||
// Data processing
|
||||
|
||||
pub fn @"and"(cond: Condition, s: u1, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .@"and", s, rd, rn, op2);
|
||||
}
|
||||
|
||||
pub fn eor(cond: Condition, s: u1, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .eor, s, rd, rn, op2);
|
||||
}
|
||||
|
||||
pub fn sub(cond: Condition, s: u1, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .sub, s, rd, rn, op2);
|
||||
}
|
||||
|
||||
pub fn rsb(cond: Condition, s: u1, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .rsb, s, rd, rn, op2);
|
||||
}
|
||||
|
||||
pub fn add(cond: Condition, s: u1, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .add, s, rd, rn, op2);
|
||||
}
|
||||
|
||||
pub fn adc(cond: Condition, s: u1, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .adc, s, rd, rn, op2);
|
||||
}
|
||||
|
||||
pub fn sbc(cond: Condition, s: u1, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .sbc, s, rd, rn, op2);
|
||||
}
|
||||
|
||||
pub fn rsc(cond: Condition, s: u1, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .rsc, s, rd, rn, op2);
|
||||
}
|
||||
|
||||
pub fn tst(cond: Condition, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .tst, 1, .r0, rn, op2);
|
||||
}
|
||||
|
||||
pub fn teq(cond: Condition, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .teq, 1, .r0, rn, op2);
|
||||
}
|
||||
|
||||
pub fn cmp(cond: Condition, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .cmp, 1, .r0, rn, op2);
|
||||
}
|
||||
|
||||
pub fn cmn(cond: Condition, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .cmn, 1, .r0, rn, op2);
|
||||
}
|
||||
|
||||
pub fn orr(cond: Condition, s: u1, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .orr, s, rd, rn, op2);
|
||||
}
|
||||
|
||||
pub fn mov(cond: Condition, s: u1, rd: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .mov, s, rd, .r0, op2);
|
||||
}
|
||||
|
||||
pub fn bic(cond: Condition, s: u1, rd: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .bic, s, rd, rn, op2);
|
||||
}
|
||||
|
||||
pub fn mvn(cond: Condition, s: u1, rd: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .mvn, s, rd, .r0, op2);
|
||||
}
|
||||
|
||||
// Single data transfer
|
||||
|
||||
pub fn ldr(cond: Condition, rd: Register, rn: Register, offset: Offset) Instruction {
|
||||
return singleDataTransfer(cond, rd, rn, offset, 1, 1, 0, 0, 1);
|
||||
}
|
||||
|
||||
pub fn str(cond: Condition, rd: Register, rn: Register, offset: Offset) Instruction {
|
||||
return singleDataTransfer(cond, rd, rn, offset, 1, 1, 0, 0, 0);
|
||||
}
|
||||
|
||||
// Branch
|
||||
|
||||
pub fn b(cond: Condition, offset: i24) Instruction {
|
||||
return branch(cond, offset, 0);
|
||||
}
|
||||
|
||||
pub fn bl(cond: Condition, offset: i24) Instruction {
|
||||
return branch(cond, offset, 1);
|
||||
}
|
||||
|
||||
// Branch and exchange
|
||||
|
||||
pub fn bx(cond: Condition, rn: Register) Instruction {
|
||||
return branchExchange(cond, rn, 0);
|
||||
}
|
||||
|
||||
pub fn blx(cond: Condition, rn: Register) Instruction {
|
||||
return branchExchange(cond, rn, 1);
|
||||
}
|
||||
|
||||
// Supervisor Call
|
||||
|
||||
pub const swi = svc;
|
||||
|
||||
pub fn svc(cond: Condition, comment: u24) Instruction {
|
||||
return supervisorCall(cond, comment);
|
||||
}
|
||||
|
||||
// Breakpoint
|
||||
|
||||
pub fn bkpt(imm: u16) Instruction {
|
||||
return breakpoint(imm);
|
||||
}
|
||||
};
|
||||
|
||||
test "serialize instructions" {
|
||||
const Testcase = struct {
|
||||
inst: Instruction,
|
||||
expected: u32,
|
||||
};
|
||||
|
||||
const testcases = [_]Testcase{
|
||||
.{ // add r0, r0, r0
|
||||
.inst = Instruction.add(.al, 0, .r0, .r0, Instruction.Operand.reg(.r0, Instruction.Operand.Shift.none)),
|
||||
.expected = 0b1110_00_0_0100_0_0000_0000_00000000_0000,
|
||||
},
|
||||
.{ // mov r4, r2
|
||||
.inst = Instruction.mov(.al, 0, .r4, Instruction.Operand.reg(.r2, Instruction.Operand.Shift.none)),
|
||||
.expected = 0b1110_00_0_1101_0_0000_0100_00000000_0010,
|
||||
},
|
||||
.{ // mov r0, #42
|
||||
.inst = Instruction.mov(.al, 0, .r0, Instruction.Operand.imm(42, 0)),
|
||||
.expected = 0b1110_00_1_1101_0_0000_0000_0000_00101010,
|
||||
},
|
||||
.{ // ldr r0, [r2, #42]
|
||||
.inst = Instruction.ldr(.al, .r0, .r2, Instruction.Offset.imm(42)),
|
||||
.expected = 0b1110_01_0_1_1_0_0_1_0010_0000_000000101010,
|
||||
},
|
||||
.{ // str r0, [r3]
|
||||
.inst = Instruction.str(.al, .r0, .r3, Instruction.Offset.none),
|
||||
.expected = 0b1110_01_0_1_1_0_0_0_0011_0000_000000000000,
|
||||
},
|
||||
.{ // b #12
|
||||
.inst = Instruction.b(.al, 12),
|
||||
.expected = 0b1110_101_0_0000_0000_0000_0000_0000_1100,
|
||||
},
|
||||
.{ // bl #-4
|
||||
.inst = Instruction.bl(.al, -4),
|
||||
.expected = 0b1110_101_1_1111_1111_1111_1111_1111_1100,
|
||||
},
|
||||
.{ // bx lr
|
||||
.inst = Instruction.bx(.al, .lr),
|
||||
.expected = 0b1110_0001_0010_1111_1111_1111_0001_1110,
|
||||
},
|
||||
.{ // svc #0
|
||||
.inst = Instruction.svc(.al, 0),
|
||||
.expected = 0b1110_1111_0000_0000_0000_0000_0000_0000,
|
||||
},
|
||||
.{ // bkpt #42
|
||||
.inst = Instruction.bkpt(42),
|
||||
.expected = 0b1110_0001_0010_000000000010_0111_1010,
|
||||
},
|
||||
};
|
||||
|
||||
for (testcases) |case| {
|
||||
const actual = case.inst.toU32();
|
||||
testing.expectEqual(case.expected, actual);
|
||||
}
|
||||
}
|
||||
@ -756,6 +756,7 @@ pub const Type = extern union {
|
||||
.fn_ccc_void_no_args, // represents machine code; not a pointer
|
||||
.function, // represents machine code; not a pointer
|
||||
=> return switch (target.cpu.arch) {
|
||||
.arm => 4,
|
||||
.riscv64 => 2,
|
||||
else => 1,
|
||||
},
|
||||
|
||||
@ -18,6 +18,11 @@ const linux_riscv64 = std.zig.CrossTarget{
|
||||
.os_tag = .linux,
|
||||
};
|
||||
|
||||
const linux_arm = std.zig.CrossTarget{
|
||||
.cpu_arch = .arm,
|
||||
.os_tag = .linux,
|
||||
};
|
||||
|
||||
const wasi = std.zig.CrossTarget{
|
||||
.cpu_arch = .wasm32,
|
||||
.os_tag = .wasi,
|
||||
@ -181,6 +186,41 @@ pub fn addCases(ctx: *TestContext) !void {
|
||||
);
|
||||
}
|
||||
|
||||
{
|
||||
var case = ctx.exe("hello world", linux_arm);
|
||||
// Regular old hello world
|
||||
case.addCompareOutput(
|
||||
\\export fn _start() noreturn {
|
||||
\\ print();
|
||||
\\ exit();
|
||||
\\}
|
||||
\\
|
||||
\\fn print() void {
|
||||
\\ asm volatile ("svc #0"
|
||||
\\ :
|
||||
\\ : [number] "{r7}" (4),
|
||||
\\ [arg1] "{r0}" (1),
|
||||
\\ [arg2] "{r1}" (@ptrToInt("Hello, World!\n")),
|
||||
\\ [arg3] "{r2}" (14)
|
||||
\\ : "memory"
|
||||
\\ );
|
||||
\\ return;
|
||||
\\}
|
||||
\\
|
||||
\\fn exit() noreturn {
|
||||
\\ asm volatile ("svc #0"
|
||||
\\ :
|
||||
\\ : [number] "{r7}" (1),
|
||||
\\ [arg1] "{r0}" (0)
|
||||
\\ : "memory"
|
||||
\\ );
|
||||
\\ unreachable;
|
||||
\\}
|
||||
,
|
||||
"Hello, World!\n",
|
||||
);
|
||||
}
|
||||
|
||||
{
|
||||
var case = ctx.exe("adding numbers at comptime", linux_x64);
|
||||
case.addCompareOutput(
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user