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test: Disable vector division operators on RISC-V with vector support

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https://github.com/ziglang/zig/issues/24301
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Alex Rønne Petersen 2025-06-30 07:04:35 +02:00
parent 1fcabe0bfc
commit 1f2e3b39ae
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test/behavior/vector.zig
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@ -560,6 +560,7 @@ test "vector division operators" {
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_spirv) return error.SkipZigTest;
if (comptime builtin.cpu.has(.riscv, .v) and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/24301
const S = struct {
fn doTheTestDiv(comptime T: type, x: @Vector(4, T), y: @Vector(4, T)) !void {