mirror/zig
1
0
Fork 0
mirror of https://github.com/ziglang/zig.git synced 2026-02-13 04:48:20 +00:00
Code Issues Packages Projects Releases Wiki Activity

compiler-rt: Always use f16 as the half type for riscv.

Browse Source
This commit is contained in:
Alex Rønne Petersen 2024-10-06 11:55:44 +02:00
parent 958f57d65d
commit 0941364d70
No known key found for this signature in database
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/compiler_rt/common.zig
View File

@ -103,7 +103,7 @@ pub fn F16T(comptime OtherType: type) type {
else
u16,
.aarch64, .aarch64_be => f16,
.riscv64 => if (builtin.zig_backend == .stage1) u16 else f16,
.riscv32, .riscv64 => f16,
.x86, .x86_64 => if (builtin.target.isDarwin()) switch (OtherType) {
// Starting with LLVM 16, Darwin uses different abi for f16
// depending on the type of the other return/argument..???