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x86_64: enable integer vector registers

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This commit is contained in:
Jacob Young 2023-05-14 17:26:44 -04:00
parent 6c6d8d67cf
commit 037bf1a580
1 changed files with 3 additions and 3 deletions
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6
src/arch/x86_64/CodeGen.zig
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@ -2261,11 +2261,11 @@ fn allocRegOrMemAdvanced(self: *Self, ty: Type, inst: ?Air.Inst.Index, reg_ok: b
},
.Vector => switch (ty.childType().zigTypeTag()) {
.Float => switch (ty.childType().floatBits(self.target.*)) {
16, 32, 64 => if (self.hasFeature(.avx)) 32 else 16,
80, 128 => break :need_mem,
16, 32, 64, 128 => if (self.hasFeature(.avx)) 32 else 16,
80 => break :need_mem,
else => unreachable,
},
else => break :need_mem,
else => if (self.hasFeature(.avx)) 32 else 16,
},
else => 8,
})) {