From 037bf1a580fe24b427e0ee5f7aecfec7202c1bf3 Mon Sep 17 00:00:00 2001
From: Jacob Young <jacobly0@users.noreply.github.com>
Date: Sun, 14 May 2023 17:26:44 -0400
Subject: [PATCH] x86_64: enable integer vector registers

---
 src/arch/x86_64/CodeGen.zig | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/arch/x86_64/CodeGen.zig b/src/arch/x86_64/CodeGen.zig
index 80f537e046..51e86447dc 100644
--- a/src/arch/x86_64/CodeGen.zig
+++ b/src/arch/x86_64/CodeGen.zig
@@ -2261,11 +2261,11 @@ fn allocRegOrMemAdvanced(self: *Self, ty: Type, inst: ?Air.Inst.Index, reg_ok: b
             },
             .Vector => switch (ty.childType().zigTypeTag()) {
                 .Float => switch (ty.childType().floatBits(self.target.*)) {
-                    16, 32, 64 => if (self.hasFeature(.avx)) 32 else 16,
-                    80, 128 => break :need_mem,
+                    16, 32, 64, 128 => if (self.hasFeature(.avx)) 32 else 16,
+                    80 => break :need_mem,
                     else => unreachable,
                 },
-                else => break :need_mem,
+                else => if (self.hasFeature(.avx)) 32 else 16,
             },
             else => 8,
         })) {