mirror of
https://github.com/ziglang/zig.git
synced 2025-12-28 17:13:19 +00:00
332eafeb7f
Ran into a design flaw here which will need to get solved by having AstGen annotate ZIR with which instructions are closed over.
124 lines
3.2 KiB
Zig
124 lines
3.2 KiB
Zig
const std = @import("std");
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const DW = std.dwarf;
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// zig fmt: off
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pub const Register = enum(u8) {
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// 0 through 7, 32-bit registers. id is int value
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eax, ecx, edx, ebx, esp, ebp, esi, edi,
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// 8-15, 16-bit registers. id is int value - 8.
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ax, cx, dx, bx, sp, bp, si, di,
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// 16-23, 8-bit registers. id is int value - 16.
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al, cl, dl, bl, ah, ch, dh, bh,
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/// Returns the bit-width of the register.
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pub fn size(self: @This()) u7 {
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return switch (@enumToInt(self)) {
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0...7 => 32,
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8...15 => 16,
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16...23 => 8,
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else => unreachable,
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};
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}
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/// Returns the register's id. This is used in practically every opcode the
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/// x86 has. It is embedded in some instructions, such as the `B8 +rd` move
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/// instruction, and is used in the R/M byte.
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pub fn id(self: @This()) u3 {
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return @truncate(u3, @enumToInt(self));
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}
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/// Returns the index into `callee_preserved_regs`.
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pub fn allocIndex(self: Register) ?u4 {
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return switch (self) {
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.eax, .ax, .al => 0,
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.ecx, .cx, .cl => 1,
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.edx, .dx, .dl => 2,
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.esi, .si => 3,
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.edi, .di => 4,
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else => null,
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};
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}
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/// Convert from any register to its 32 bit alias.
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pub fn to32(self: Register) Register {
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return @intToEnum(Register, @as(u8, self.id()));
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}
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/// Convert from any register to its 16 bit alias.
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pub fn to16(self: Register) Register {
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return @intToEnum(Register, @as(u8, self.id()) + 8);
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}
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/// Convert from any register to its 8 bit alias.
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pub fn to8(self: Register) Register {
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return @intToEnum(Register, @as(u8, self.id()) + 16);
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}
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pub fn dwarfLocOp(reg: Register) u8 {
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return switch (reg.to32()) {
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.eax => DW.OP.reg0,
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.ecx => DW.OP.reg1,
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.edx => DW.OP.reg2,
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.ebx => DW.OP.reg3,
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.esp => DW.OP.reg4,
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.ebp => DW.OP.reg5,
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.esi => DW.OP.reg6,
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.edi => DW.OP.reg7,
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else => unreachable,
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};
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}
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};
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// zig fmt: on
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pub const callee_preserved_regs = [_]Register{ .eax, .ecx, .edx, .esi, .edi };
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// TODO add these to Register enum and corresponding dwarfLocOp
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// // Return Address register. This is stored in `0(%esp, "")` and is not a physical register.
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// RA = (8, "RA"),
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//
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// ST0 = (11, "st0"),
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// ST1 = (12, "st1"),
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// ST2 = (13, "st2"),
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// ST3 = (14, "st3"),
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// ST4 = (15, "st4"),
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// ST5 = (16, "st5"),
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// ST6 = (17, "st6"),
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// ST7 = (18, "st7"),
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//
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// XMM0 = (21, "xmm0"),
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// XMM1 = (22, "xmm1"),
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// XMM2 = (23, "xmm2"),
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// XMM3 = (24, "xmm3"),
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// XMM4 = (25, "xmm4"),
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// XMM5 = (26, "xmm5"),
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// XMM6 = (27, "xmm6"),
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// XMM7 = (28, "xmm7"),
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//
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// MM0 = (29, "mm0"),
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// MM1 = (30, "mm1"),
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// MM2 = (31, "mm2"),
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// MM3 = (32, "mm3"),
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// MM4 = (33, "mm4"),
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// MM5 = (34, "mm5"),
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// MM6 = (35, "mm6"),
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// MM7 = (36, "mm7"),
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//
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// MXCSR = (39, "mxcsr"),
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//
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// ES = (40, "es"),
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// CS = (41, "cs"),
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// SS = (42, "ss"),
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// DS = (43, "ds"),
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// FS = (44, "fs"),
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// GS = (45, "gs"),
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//
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// TR = (48, "tr"),
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// LDTR = (49, "ldtr"),
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//
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// FS_BASE = (93, "fs.base"),
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// GS_BASE = (94, "gs.base"),
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