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zig
/
src
/
arch
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joachimschmidt557
f48f4baf67
stage2 ARM: generate correct variants of ldr instruction
...
When loading an i16 for example, generate ldrsh instead of ldrh
2022-02-26 13:00:01 +01:00
..
aarch64
x64+aarch64: check for pointer to zero-bit type when lowering decl
2022-02-25 21:59:19 +01:00
arm
stage2 ARM: generate correct variants of ldr instruction
2022-02-26 13:00:01 +01:00
riscv64
stage2: implement fieldParentPtr
2022-02-24 19:48:34 +02:00
wasm
wasm: Fix error union's size/alignment
2022-02-25 09:33:15 +01:00
x86
stage2,x86_64: revert fixing callee preserved regs
2021-11-19 22:18:56 +01:00
x86_64
x64+aarch64: check for pointer to zero-bit type when lowering decl
2022-02-25 21:59:19 +01:00
