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d17f492017
* Breaking language change: inline assembly must use string literal
syntax. This is in preparation for inline assembly improvements that
involve more integration with the Zig language. This means we cannot
rely on text substitution.
* Liveness: properly handle inline assembly and function calls with
more than 3 operands.
- More than 35 operands is not yet supported. This is a low priority
to implement.
- This required implementation in codegen.zig as well.
* Liveness: fix bug causing incorrect tomb bits.
* Sema: enable switch expressions that are evaluated at compile-time.
- Runtime switch instructions still need to be reworked in this
branch. There was a TODO left here (by me) with a suggestion to do
some bigger changes as part of the AIR memory reworking. Now that
time has come and I plan to honor the suggestion in a future commit
before merging this branch.
* AIR printing: fix missing ')' on alive instructions.
We're back to "hello world" working for the x86_64 backend.
89 lines
3.2 KiB
Zig
89 lines
3.2 KiB
Zig
// SPDX-License-Identifier: MIT
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// Copyright (c) 2015-2021 Zig Contributors
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// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
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// The MIT license requires this copyright notice to be included in all copies
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// and substantial portions of the software.
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const std = @import("std.zig");
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const target = std.Target.current;
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pub const Ordering = std.builtin.AtomicOrder;
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pub const Stack = @import("atomic/stack.zig").Stack;
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pub const Queue = @import("atomic/queue.zig").Queue;
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pub const Atomic = @import("atomic/Atomic.zig").Atomic;
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test "std.atomic" {
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_ = @import("atomic/stack.zig");
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_ = @import("atomic/queue.zig");
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_ = @import("atomic/Atomic.zig");
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}
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pub inline fn fence(comptime ordering: Ordering) void {
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switch (ordering) {
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.Acquire, .Release, .AcqRel, .SeqCst => {
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@fence(ordering);
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},
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else => {
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@compileLog(ordering, " only applies to a given memory location");
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},
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}
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}
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pub inline fn compilerFence(comptime ordering: Ordering) void {
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switch (ordering) {
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.Acquire, .Release, .AcqRel, .SeqCst => asm volatile ("" ::: "memory"),
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else => @compileLog(ordering, " only applies to a given memory location"),
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}
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}
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test "fence/compilerFence" {
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inline for (.{ .Acquire, .Release, .AcqRel, .SeqCst }) |ordering| {
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compilerFence(ordering);
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fence(ordering);
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}
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}
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/// Signals to the processor that the caller is inside a busy-wait spin-loop.
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pub inline fn spinLoopHint() void {
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switch (target.cpu.arch) {
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// No-op instruction that can hint to save (or share with a hardware-thread)
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// pipelining/power resources
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// https://software.intel.com/content/www/us/en/develop/articles/benefitting-power-and-performance-sleep-loops.html
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.i386, .x86_64 => asm volatile ("pause" ::: "memory"),
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// No-op instruction that serves as a hardware-thread resource yield hint.
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// https://stackoverflow.com/a/7588941
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.powerpc64, .powerpc64le => asm volatile ("or 27, 27, 27" ::: "memory"),
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// `isb` appears more reliable for releasing execution resources than `yield`
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// on common aarch64 CPUs.
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// https://bugs.java.com/bugdatabase/view_bug.do?bug_id=8258604
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// https://bugs.mysql.com/bug.php?id=100664
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.aarch64, .aarch64_be, .aarch64_32 => asm volatile ("isb" ::: "memory"),
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// `yield` was introduced in v6k but is also available on v6m.
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// https://www.keil.com/support/man/docs/armasm/armasm_dom1361289926796.htm
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.arm, .armeb, .thumb, .thumbeb => {
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const can_yield = comptime std.Target.arm.featureSetHasAny(target.cpu.features, .{
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.has_v6k, .has_v6m,
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});
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if (can_yield) {
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asm volatile ("yield" ::: "memory");
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} else {
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asm volatile ("" ::: "memory");
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}
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},
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// Memory barrier to prevent the compiler from optimizing away the spin-loop
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// even if no hint_instruction was provided.
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else => asm volatile ("" ::: "memory"),
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}
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}
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test "spinLoopHint" {
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var i: usize = 10;
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while (i > 0) : (i -= 1) {
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spinLoopHint();
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}
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}
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