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zig/src/codegen
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Andrew Kelley bdbedff910 stage2: LLVM backend: properly set module target data 
Also fix tripping LLVM assert having to do with 0 bit integers.
stage2 behavior tests now run clean in a debug build of llvm 12.
2021-09-29 15:33:45 -07:00
..
llvm
stage2: LLVM backend: properly set module target data
2021-09-29 15:33:45 -07:00
spirv
stage2: update for new usingnamespace semantics
2021-09-01 17:54:07 -07:00
c.zig
stage2: implement @clz and @ctz
2021-09-28 22:38:51 -07:00
llvm.zig
stage2: LLVM backend: properly set module target data
2021-09-29 15:33:45 -07:00
spirv.zig
Spelling corrections (#9833)
2021-09-24 13:39:20 -04:00
wasm.zig
Spelling corrections (#9833)
2021-09-24 13:39:20 -04:00