mirror of
https://github.com/ziglang/zig.git
synced 2026-01-26 17:25:25 +00:00
412 lines
15 KiB
Zig
412 lines
15 KiB
Zig
const std = @import("std");
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const mem = std.mem;
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const io = std.io;
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const fs = std.fs;
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const fmt = std.fmt;
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const testing = std.testing;
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const Target = std.Target;
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const CrossTarget = std.zig.CrossTarget;
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const assert = std.debug.assert;
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const SparcCpuinfoImpl = struct {
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model: ?*const Target.Cpu.Model = null,
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is_64bit: bool = false,
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const cpu_names = .{
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.{ "SuperSparc", &Target.sparc.cpu.supersparc },
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.{ "HyperSparc", &Target.sparc.cpu.hypersparc },
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.{ "SpitFire", &Target.sparc.cpu.ultrasparc },
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.{ "BlackBird", &Target.sparc.cpu.ultrasparc },
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.{ "Sabre", &Target.sparc.cpu.ultrasparc },
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.{ "Hummingbird", &Target.sparc.cpu.ultrasparc },
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.{ "Cheetah", &Target.sparc.cpu.ultrasparc3 },
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.{ "Jalapeno", &Target.sparc.cpu.ultrasparc3 },
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.{ "Jaguar", &Target.sparc.cpu.ultrasparc3 },
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.{ "Panther", &Target.sparc.cpu.ultrasparc3 },
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.{ "Serrano", &Target.sparc.cpu.ultrasparc3 },
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.{ "UltraSparc T1", &Target.sparc.cpu.niagara },
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.{ "UltraSparc T2", &Target.sparc.cpu.niagara2 },
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.{ "UltraSparc T3", &Target.sparc.cpu.niagara3 },
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.{ "UltraSparc T4", &Target.sparc.cpu.niagara4 },
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.{ "UltraSparc T5", &Target.sparc.cpu.niagara4 },
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.{ "LEON", &Target.sparc.cpu.leon3 },
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};
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fn line_hook(self: *SparcCpuinfoImpl, key: []const u8, value: []const u8) !bool {
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if (mem.eql(u8, key, "cpu")) {
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inline for (cpu_names) |pair| {
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if (mem.indexOfPos(u8, value, 0, pair[0]) != null) {
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self.model = pair[1];
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break;
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}
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}
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} else if (mem.eql(u8, key, "type")) {
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self.is_64bit = mem.eql(u8, value, "sun4u") or mem.eql(u8, value, "sun4v");
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}
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return true;
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}
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fn finalize(self: *const SparcCpuinfoImpl, arch: Target.Cpu.Arch) ?Target.Cpu {
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// At the moment we only support 64bit SPARC systems.
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assert(self.is_64bit);
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const model = self.model orelse return null;
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return Target.Cpu{
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.arch = arch,
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.model = model,
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.features = model.features,
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};
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}
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};
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const SparcCpuinfoParser = CpuinfoParser(SparcCpuinfoImpl);
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test "cpuinfo: SPARC" {
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try testParser(SparcCpuinfoParser, .sparcv9, &Target.sparc.cpu.niagara2,
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\\cpu : UltraSparc T2 (Niagara2)
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\\fpu : UltraSparc T2 integrated FPU
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\\pmu : niagara2
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\\type : sun4v
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);
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}
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const PowerpcCpuinfoImpl = struct {
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model: ?*const Target.Cpu.Model = null,
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const cpu_names = .{
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.{ "604e", &Target.powerpc.cpu.@"604e" },
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.{ "604", &Target.powerpc.cpu.@"604" },
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.{ "7400", &Target.powerpc.cpu.@"7400" },
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.{ "7410", &Target.powerpc.cpu.@"7400" },
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.{ "7447", &Target.powerpc.cpu.@"7400" },
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.{ "7455", &Target.powerpc.cpu.@"7450" },
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.{ "G4", &Target.powerpc.cpu.@"g4" },
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.{ "POWER4", &Target.powerpc.cpu.@"970" },
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.{ "PPC970FX", &Target.powerpc.cpu.@"970" },
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.{ "PPC970MP", &Target.powerpc.cpu.@"970" },
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.{ "G5", &Target.powerpc.cpu.@"g5" },
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.{ "POWER5", &Target.powerpc.cpu.@"g5" },
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.{ "A2", &Target.powerpc.cpu.@"a2" },
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.{ "POWER6", &Target.powerpc.cpu.@"pwr6" },
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.{ "POWER7", &Target.powerpc.cpu.@"pwr7" },
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.{ "POWER8", &Target.powerpc.cpu.@"pwr8" },
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.{ "POWER8E", &Target.powerpc.cpu.@"pwr8" },
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.{ "POWER8NVL", &Target.powerpc.cpu.@"pwr8" },
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.{ "POWER9", &Target.powerpc.cpu.@"pwr9" },
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.{ "POWER10", &Target.powerpc.cpu.@"pwr10" },
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};
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fn line_hook(self: *PowerpcCpuinfoImpl, key: []const u8, value: []const u8) !bool {
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if (mem.eql(u8, key, "cpu")) {
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// The model name is often followed by a comma or space and extra
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// info.
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inline for (cpu_names) |pair| {
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const end_index = mem.indexOfAny(u8, value, ", ") orelse value.len;
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if (mem.eql(u8, value[0..end_index], pair[0])) {
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self.model = pair[1];
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break;
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}
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}
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// Stop the detection once we've seen the first core.
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return false;
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}
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return true;
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}
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fn finalize(self: *const PowerpcCpuinfoImpl, arch: Target.Cpu.Arch) ?Target.Cpu {
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const model = self.model orelse return null;
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return Target.Cpu{
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.arch = arch,
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.model = model,
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.features = model.features,
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};
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}
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};
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const PowerpcCpuinfoParser = CpuinfoParser(PowerpcCpuinfoImpl);
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test "cpuinfo: PowerPC" {
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try testParser(PowerpcCpuinfoParser, .powerpc, &Target.powerpc.cpu.@"970",
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\\processor : 0
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\\cpu : PPC970MP, altivec supported
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\\clock : 1250.000000MHz
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\\revision : 1.1 (pvr 0044 0101)
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);
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try testParser(PowerpcCpuinfoParser, .powerpc64le, &Target.powerpc.cpu.pwr8,
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\\processor : 0
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\\cpu : POWER8 (raw), altivec supported
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\\clock : 2926.000000MHz
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\\revision : 2.0 (pvr 004d 0200)
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);
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}
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const ArmCpuinfoImpl = struct {
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cores: [4]CoreInfo = undefined,
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core_no: usize = 0,
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have_fields: usize = 0,
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const CoreInfo = struct {
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architecture: u8 = 0,
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implementer: u8 = 0,
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variant: u8 = 0,
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part: u16 = 0,
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is_really_v6: bool = false,
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};
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const cpu_models = struct {
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// Shorthands to simplify the tables below.
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const A32 = Target.arm.cpu;
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const A64 = Target.aarch64.cpu;
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// implementer = 0x41
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const ARM = .{
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.{ 0x926, &A32.arm926ej_s, null },
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.{ 0xb02, &A32.mpcore, null },
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.{ 0xb36, &A32.arm1136j_s, null },
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.{ 0xb56, &A32.arm1156t2_s, null },
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.{ 0xb76, &A32.arm1176jz_s, null },
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.{ 0xc05, &A32.cortex_a5, null },
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.{ 0xc07, &A32.cortex_a7, null },
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.{ 0xc08, &A32.cortex_a8, null },
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.{ 0xc09, &A32.cortex_a9, null },
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.{ 0xc0d, &A32.cortex_a17, null },
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.{ 0xc0f, &A32.cortex_a15, null },
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.{ 0xc0e, &A32.cortex_a17, null },
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.{ 0xc14, &A32.cortex_r4, null },
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.{ 0xc15, &A32.cortex_r5, null },
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.{ 0xc17, &A32.cortex_r7, null },
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.{ 0xc18, &A32.cortex_r8, null },
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.{ 0xc20, &A32.cortex_m0, null },
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.{ 0xc21, &A32.cortex_m1, null },
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.{ 0xc23, &A32.cortex_m3, null },
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.{ 0xc24, &A32.cortex_m4, null },
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.{ 0xc27, &A32.cortex_m7, null },
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.{ 0xc60, &A32.cortex_m0plus, null },
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.{ 0xd01, &A32.cortex_a32, null },
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.{ 0xd03, &A32.cortex_a53, &A64.cortex_a53 },
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.{ 0xd04, &A32.cortex_a35, &A64.cortex_a35 },
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.{ 0xd05, &A32.cortex_a55, &A64.cortex_a55 },
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.{ 0xd07, &A32.cortex_a57, &A64.cortex_a57 },
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.{ 0xd08, &A32.cortex_a72, &A64.cortex_a72 },
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.{ 0xd09, &A32.cortex_a73, &A64.cortex_a73 },
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.{ 0xd0a, &A32.cortex_a75, &A64.cortex_a75 },
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.{ 0xd0b, &A32.cortex_a76, &A64.cortex_a76 },
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.{ 0xd0c, &A32.neoverse_n1, null },
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.{ 0xd0d, &A32.cortex_a77, &A64.cortex_a77 },
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.{ 0xd13, &A32.cortex_r52, null },
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.{ 0xd20, &A32.cortex_m23, null },
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.{ 0xd21, &A32.cortex_m33, null },
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.{ 0xd41, &A32.cortex_a78, &A64.cortex_a78 },
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.{ 0xd4b, &A32.cortex_a78c, &A64.cortex_a78c },
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.{ 0xd44, &A32.cortex_x1, &A64.cortex_x1 },
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.{ 0xd02, null, &A64.cortex_a34 },
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.{ 0xd06, null, &A64.cortex_a65 },
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.{ 0xd43, null, &A64.cortex_a65ae },
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};
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fn isKnown(implementer: u8, part: u16, is_64bit: bool) ?*const Target.Cpu.Model {
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const models = switch (implementer) {
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0x41 => ARM,
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else => return null,
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};
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inline for (models) |model| {
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if (model[0] == part)
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return if (is_64bit) model[2] else model[1];
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}
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return null;
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}
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};
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fn addOne(self: *ArmCpuinfoImpl) void {
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if (self.have_fields == 4 and self.core_no < self.cores.len) {
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if (self.core_no > 0) {
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// Deduplicate the core info.
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for (self.cores[0..self.core_no]) |it| {
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if (std.meta.eql(it, self.cores[self.core_no]))
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return;
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}
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}
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self.core_no += 1;
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}
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}
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fn line_hook(self: *ArmCpuinfoImpl, key: []const u8, value: []const u8) !bool {
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const info = &self.cores[self.core_no];
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if (mem.eql(u8, key, "processor")) {
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// Handle both old-style and new-style cpuinfo formats.
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// The former prints a sequence of "processor: N" lines for each
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// core and then the info for the core that's executing this code(!)
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// while the latter prints the infos for each core right after the
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// "processor" key.
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self.have_fields = 0;
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self.cores[self.core_no] = .{};
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} else if (mem.eql(u8, key, "CPU implementer")) {
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info.implementer = try fmt.parseInt(u8, value, 0);
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self.have_fields += 1;
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} else if (mem.eql(u8, key, "CPU architecture")) {
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// "AArch64" on older kernels.
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info.architecture = if (mem.startsWith(u8, value, "AArch64"))
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8
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else
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try fmt.parseInt(u8, value, 0);
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self.have_fields += 1;
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} else if (mem.eql(u8, key, "CPU variant")) {
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info.variant = try fmt.parseInt(u8, value, 0);
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self.have_fields += 1;
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} else if (mem.eql(u8, key, "CPU part")) {
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info.part = try fmt.parseInt(u16, value, 0);
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self.have_fields += 1;
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} else if (mem.eql(u8, key, "model name")) {
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// ARMv6 cores report "CPU architecture" equal to 7.
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if (mem.indexOf(u8, value, "(v6l)")) |_| {
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info.is_really_v6 = true;
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}
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} else if (mem.eql(u8, key, "CPU revision")) {
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// This field is always the last one for each CPU section.
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_ = self.addOne();
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}
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return true;
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}
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fn finalize(self: *ArmCpuinfoImpl, arch: Target.Cpu.Arch) ?Target.Cpu {
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if (self.core_no == 0) return null;
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const is_64bit = switch (arch) {
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.aarch64, .aarch64_be, .aarch64_32 => true,
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else => false,
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};
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var known_models: [self.cores.len]?*const Target.Cpu.Model = undefined;
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for (self.cores[0..self.core_no]) |core, i| {
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known_models[i] =
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cpu_models.isKnown(core.implementer, core.part, is_64bit);
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}
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// XXX We pick the first core on big.LITTLE systems, hopefully the
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// LITTLE one.
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const model = known_models[0] orelse return null;
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return Target.Cpu{
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.arch = arch,
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.model = model,
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.features = model.features,
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};
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}
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};
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const ArmCpuinfoParser = CpuinfoParser(ArmCpuinfoImpl);
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test "cpuinfo: ARM" {
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try testParser(ArmCpuinfoParser, .arm, &Target.arm.cpu.arm1176jz_s,
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\\processor : 0
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\\model name : ARMv6-compatible processor rev 7 (v6l)
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\\BogoMIPS : 997.08
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\\Features : half thumb fastmult vfp edsp java tls
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\\CPU implementer : 0x41
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\\CPU architecture: 7
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\\CPU variant : 0x0
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\\CPU part : 0xb76
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\\CPU revision : 7
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);
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try testParser(ArmCpuinfoParser, .arm, &Target.arm.cpu.cortex_a7,
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\\processor : 0
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\\model name : ARMv7 Processor rev 3 (v7l)
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\\BogoMIPS : 18.00
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\\Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae
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\\CPU implementer : 0x41
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\\CPU architecture: 7
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\\CPU variant : 0x0
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\\CPU part : 0xc07
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\\CPU revision : 3
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\\
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\\processor : 4
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\\model name : ARMv7 Processor rev 3 (v7l)
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\\BogoMIPS : 90.00
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\\Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae
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\\CPU implementer : 0x41
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\\CPU architecture: 7
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\\CPU variant : 0x2
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\\CPU part : 0xc0f
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\\CPU revision : 3
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);
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try testParser(ArmCpuinfoParser, .aarch64, &Target.aarch64.cpu.cortex_a72,
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\\processor : 0
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\\BogoMIPS : 108.00
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\\Features : fp asimd evtstrm crc32 cpuid
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\\CPU implementer : 0x41
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\\CPU architecture: 8
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\\CPU variant : 0x0
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\\CPU part : 0xd08
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\\CPU revision : 3
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);
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}
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fn testParser(
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parser: anytype,
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arch: Target.Cpu.Arch,
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expected_model: *const Target.Cpu.Model,
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input: []const u8,
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) !void {
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var fbs = io.fixedBufferStream(input);
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const result = try parser.parse(arch, fbs.reader());
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testing.expectEqual(expected_model, result.?.model);
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testing.expect(expected_model.features.eql(result.?.features));
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}
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// The generic implementation of a /proc/cpuinfo parser.
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// For every line it invokes the line_hook method with the key and value strings
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// as first and second parameters. Returning false from the hook function stops
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// the iteration without raising an error.
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// When all the lines have been analyzed the finalize method is called.
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fn CpuinfoParser(comptime impl: anytype) type {
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return struct {
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fn parse(arch: Target.Cpu.Arch, reader: anytype) anyerror!?Target.Cpu {
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var line_buf: [1024]u8 = undefined;
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var obj: impl = .{};
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while (true) {
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const line = (try reader.readUntilDelimiterOrEof(&line_buf, '\n')) orelse break;
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const colon_pos = mem.indexOfScalar(u8, line, ':') orelse continue;
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const key = mem.trimRight(u8, line[0..colon_pos], " \t");
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const value = mem.trimLeft(u8, line[colon_pos + 1 ..], " \t");
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if (!try obj.line_hook(key, value))
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break;
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}
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return obj.finalize(arch);
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}
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};
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}
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pub fn detectNativeCpuAndFeatures() ?Target.Cpu {
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var f = fs.openFileAbsolute("/proc/cpuinfo", .{ .intended_io_mode = .blocking }) catch |err| switch (err) {
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else => return null,
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};
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defer f.close();
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const current_arch = std.Target.current.cpu.arch;
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switch (current_arch) {
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.arm, .armeb, .thumb, .thumbeb, .aarch64, .aarch64_be, .aarch64_32 => {
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return ArmCpuinfoParser.parse(current_arch, f.reader()) catch null;
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},
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.sparcv9 => {
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return SparcCpuinfoParser.parse(current_arch, f.reader()) catch null;
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},
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.powerpc, .powerpcle, .powerpc64, .powerpc64le => {
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return PowerpcCpuinfoParser.parse(current_arch, f.reader()) catch null;
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},
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else => {},
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}
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return null;
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}
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