mirror of
https://github.com/ziglang/zig.git
synced 2025-12-27 16:43:07 +00:00
150515f44d
There is now a distinction between `@import` with a .zig extension and without. Without a .zig extension it assumes it is a package name, and returns error.PackageNotFound if not mapped into the package table.
717 lines
23 KiB
Zig
717 lines
23 KiB
Zig
const std = @import("std");
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const testing = std.testing;
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const mem = std.mem;
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const assert = std.debug.assert;
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const ArrayList = std.ArrayList;
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const Allocator = std.mem.Allocator;
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const DW = std.dwarf;
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// zig fmt: off
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/// Definitions of all of the x64 registers. The order is semantically meaningful.
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/// The registers are defined such that IDs go in descending order of 64-bit,
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/// 32-bit, 16-bit, and then 8-bit, and each set contains exactly sixteen
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/// registers. This results in some useful properties:
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///
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/// Any 64-bit register can be turned into its 32-bit form by adding 16, and
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/// vice versa. This also works between 32-bit and 16-bit forms. With 8-bit, it
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/// works for all except for sp, bp, si, and di, which do *not* have an 8-bit
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/// form.
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///
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/// If (register & 8) is set, the register is extended.
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///
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/// The ID can be easily determined by figuring out what range the register is
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/// in, and then subtracting the base.
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pub const Register = enum(u8) {
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// 0 through 15, 64-bit registers. 8-15 are extended.
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// id is just the int value.
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rax, rcx, rdx, rbx, rsp, rbp, rsi, rdi,
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r8, r9, r10, r11, r12, r13, r14, r15,
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// 16 through 31, 32-bit registers. 24-31 are extended.
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// id is int value - 16.
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eax, ecx, edx, ebx, esp, ebp, esi, edi,
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r8d, r9d, r10d, r11d, r12d, r13d, r14d, r15d,
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// 32-47, 16-bit registers. 40-47 are extended.
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// id is int value - 32.
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ax, cx, dx, bx, sp, bp, si, di,
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r8w, r9w, r10w, r11w, r12w, r13w, r14w, r15w,
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// 48-63, 8-bit registers. 56-63 are extended.
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// id is int value - 48.
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al, cl, dl, bl, ah, ch, dh, bh,
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r8b, r9b, r10b, r11b, r12b, r13b, r14b, r15b,
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/// Returns the bit-width of the register.
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pub fn size(self: Register) u7 {
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return switch (@enumToInt(self)) {
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0...15 => 64,
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16...31 => 32,
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32...47 => 16,
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48...64 => 8,
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else => unreachable,
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};
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}
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/// Returns whether the register is *extended*. Extended registers are the
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/// new registers added with amd64, r8 through r15. This also includes any
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/// other variant of access to those registers, such as r8b, r15d, and so
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/// on. This is needed because access to these registers requires special
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/// handling via the REX prefix, via the B or R bits, depending on context.
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pub fn isExtended(self: Register) bool {
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return @enumToInt(self) & 0x08 != 0;
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}
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/// This returns the 4-bit register ID, which is used in practically every
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/// opcode. Note that bit 3 (the highest bit) is *never* used directly in
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/// an instruction (@see isExtended), and requires special handling. The
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/// lower three bits are often embedded directly in instructions (such as
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/// the B8 variant of moves), or used in R/M bytes.
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pub fn id(self: Register) u4 {
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return @truncate(u4, @enumToInt(self));
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}
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/// Like id, but only returns the lower 3 bits.
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pub fn low_id(self: Register) u3 {
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return @truncate(u3, @enumToInt(self));
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}
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/// Returns the index into `callee_preserved_regs`.
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pub fn allocIndex(self: Register) ?u4 {
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return switch (self) {
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.rax, .eax, .ax, .al => 0,
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.rcx, .ecx, .cx, .cl => 1,
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.rdx, .edx, .dx, .dl => 2,
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.rsi, .esi, .si => 3,
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.rdi, .edi, .di => 4,
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.r8, .r8d, .r8w, .r8b => 5,
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.r9, .r9d, .r9w, .r9b => 6,
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.r10, .r10d, .r10w, .r10b => 7,
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.r11, .r11d, .r11w, .r11b => 8,
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else => null,
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};
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}
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/// Convert from any register to its 64 bit alias.
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pub fn to64(self: Register) Register {
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return @intToEnum(Register, self.id());
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}
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/// Convert from any register to its 32 bit alias.
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pub fn to32(self: Register) Register {
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return @intToEnum(Register, @as(u8, self.id()) + 16);
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}
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/// Convert from any register to its 16 bit alias.
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pub fn to16(self: Register) Register {
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return @intToEnum(Register, @as(u8, self.id()) + 32);
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}
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/// Convert from any register to its 8 bit alias.
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pub fn to8(self: Register) Register {
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return @intToEnum(Register, @as(u8, self.id()) + 48);
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}
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pub fn dwarfLocOp(self: Register) u8 {
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return switch (self.to64()) {
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.rax => DW.OP_reg0,
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.rdx => DW.OP_reg1,
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.rcx => DW.OP_reg2,
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.rbx => DW.OP_reg3,
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.rsi => DW.OP_reg4,
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.rdi => DW.OP_reg5,
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.rbp => DW.OP_reg6,
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.rsp => DW.OP_reg7,
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.r8 => DW.OP_reg8,
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.r9 => DW.OP_reg9,
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.r10 => DW.OP_reg10,
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.r11 => DW.OP_reg11,
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.r12 => DW.OP_reg12,
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.r13 => DW.OP_reg13,
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.r14 => DW.OP_reg14,
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.r15 => DW.OP_reg15,
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else => unreachable,
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};
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}
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};
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// zig fmt: on
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/// These registers belong to the called function.
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pub const callee_preserved_regs = [_]Register{ .rax, .rcx, .rdx, .rsi, .rdi, .r8, .r9, .r10, .r11 };
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pub const c_abi_int_param_regs = [_]Register{ .rdi, .rsi, .rdx, .rcx, .r8, .r9 };
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pub const c_abi_int_return_regs = [_]Register{ .rax, .rdx };
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/// Encoding helper functions for x86_64 instructions
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///
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/// Many of these helpers do very little, but they can help make things
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/// slightly more readable with more descriptive field names / function names.
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///
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/// Some of them also have asserts to ensure that we aren't doing dumb things.
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/// For example, trying to use register 4 (esp) in an indirect modr/m byte is illegal,
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/// you need to encode it with an SIB byte.
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///
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/// Note that ALL of these helper functions will assume capacity,
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/// so ensure that the `code` has sufficient capacity before using them.
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/// The `init` method is the recommended way to ensure capacity.
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pub const Encoder = struct {
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/// Non-owning reference to the code array
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code: *ArrayList(u8),
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const Self = @This();
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/// Wrap `code` in Encoder to make it easier to call these helper functions
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///
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/// maximum_inst_size should contain the maximum number of bytes
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/// that the encoded instruction will take.
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/// This is because the helper functions will assume capacity
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/// in order to avoid bounds checking.
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pub fn init(code: *ArrayList(u8), maximum_inst_size: u8) !Self {
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try code.ensureUnusedCapacity(maximum_inst_size);
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return Self{ .code = code };
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}
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/// Directly write a number to the code array with big endianness
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pub fn writeIntBig(self: Self, comptime T: type, value: T) void {
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mem.writeIntBig(
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T,
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self.code.addManyAsArrayAssumeCapacity(@divExact(@typeInfo(T).Int.bits, 8)),
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value,
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);
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}
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/// Directly write a number to the code array with little endianness
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pub fn writeIntLittle(self: Self, comptime T: type, value: T) void {
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mem.writeIntLittle(
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T,
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self.code.addManyAsArrayAssumeCapacity(@divExact(@typeInfo(T).Int.bits, 8)),
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value,
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);
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}
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// --------
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// Prefixes
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// --------
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pub const LegacyPrefixes = packed struct {
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/// LOCK
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prefix_f0: bool = false,
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/// REPNZ, REPNE, REP, Scalar Double-precision
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prefix_f2: bool = false,
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/// REPZ, REPE, REP, Scalar Single-precision
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prefix_f3: bool = false,
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/// CS segment override or Branch not taken
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prefix_2e: bool = false,
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/// DS segment override
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prefix_36: bool = false,
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/// ES segment override
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prefix_26: bool = false,
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/// FS segment override
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prefix_64: bool = false,
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/// GS segment override
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prefix_65: bool = false,
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/// Branch taken
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prefix_3e: bool = false,
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/// Operand size override (enables 16 bit operation)
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prefix_66: bool = false,
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/// Address size override (enables 16 bit address size)
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prefix_67: bool = false,
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padding: u5 = 0,
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};
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/// Encodes legacy prefixes
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pub fn legacyPrefixes(self: Self, prefixes: LegacyPrefixes) void {
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if (@bitCast(u16, prefixes) != 0) {
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// Hopefully this path isn't taken very often, so we'll do it the slow way for now
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// LOCK
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if (prefixes.prefix_f0) self.code.appendAssumeCapacity(0xf0);
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// REPNZ, REPNE, REP, Scalar Double-precision
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if (prefixes.prefix_f2) self.code.appendAssumeCapacity(0xf2);
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// REPZ, REPE, REP, Scalar Single-precision
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if (prefixes.prefix_f3) self.code.appendAssumeCapacity(0xf3);
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// CS segment override or Branch not taken
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if (prefixes.prefix_2e) self.code.appendAssumeCapacity(0x2e);
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// DS segment override
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if (prefixes.prefix_36) self.code.appendAssumeCapacity(0x36);
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// ES segment override
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if (prefixes.prefix_26) self.code.appendAssumeCapacity(0x26);
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// FS segment override
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if (prefixes.prefix_64) self.code.appendAssumeCapacity(0x64);
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// GS segment override
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if (prefixes.prefix_65) self.code.appendAssumeCapacity(0x65);
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// Branch taken
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if (prefixes.prefix_3e) self.code.appendAssumeCapacity(0x3e);
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// Operand size override
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if (prefixes.prefix_66) self.code.appendAssumeCapacity(0x66);
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// Address size override
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if (prefixes.prefix_67) self.code.appendAssumeCapacity(0x67);
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}
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}
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/// Use 16 bit operand size
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///
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/// Note that this flag is overridden by REX.W, if both are present.
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pub fn prefix16BitMode(self: Self) void {
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self.code.appendAssumeCapacity(0x66);
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}
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/// From section 2.2.1.2 of the manual, REX is encoded as b0100WRXB
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pub const Rex = struct {
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/// Wide, enables 64-bit operation
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w: bool = false,
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/// Extends the reg field in the ModR/M byte
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r: bool = false,
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/// Extends the index field in the SIB byte
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x: bool = false,
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/// Extends the r/m field in the ModR/M byte,
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/// or the base field in the SIB byte,
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/// or the reg field in the Opcode byte
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b: bool = false,
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};
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/// Encodes a REX prefix byte given all the fields
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///
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/// Use this byte whenever you need 64 bit operation,
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/// or one of reg, index, r/m, base, or opcode-reg might be extended.
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///
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/// See struct `Rex` for a description of each field.
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///
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/// Does not add a prefix byte if none of the fields are set!
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pub fn rex(self: Self, byte: Rex) void {
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var value: u8 = 0b0100_0000;
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if (byte.w) value |= 0b1000;
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if (byte.r) value |= 0b0100;
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if (byte.x) value |= 0b0010;
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if (byte.b) value |= 0b0001;
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if (value != 0b0100_0000) {
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self.code.appendAssumeCapacity(value);
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}
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}
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// ------
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// Opcode
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// ------
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/// Encodes a 1 byte opcode
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pub fn opcode_1byte(self: Self, opcode: u8) void {
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self.code.appendAssumeCapacity(opcode);
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}
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/// Encodes a 2 byte opcode
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///
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/// e.g. IMUL has the opcode 0x0f 0xaf, so you use
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///
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/// encoder.opcode_2byte(0x0f, 0xaf);
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pub fn opcode_2byte(self: Self, prefix: u8, opcode: u8) void {
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self.code.appendAssumeCapacity(prefix);
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self.code.appendAssumeCapacity(opcode);
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}
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/// Encodes a 1 byte opcode with a reg field
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///
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/// Remember to add a REX prefix byte if reg is extended!
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pub fn opcode_withReg(self: Self, opcode: u8, reg: u3) void {
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assert(opcode & 0b111 == 0);
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self.code.appendAssumeCapacity(opcode | reg);
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}
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// ------
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// ModR/M
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// ------
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/// Construct a ModR/M byte given all the fields
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///
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/// Remember to add a REX prefix byte if reg or rm are extended!
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pub fn modRm(self: Self, mod: u2, reg_or_opx: u3, rm: u3) void {
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self.code.appendAssumeCapacity(
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@as(u8, mod) << 6 | @as(u8, reg_or_opx) << 3 | rm,
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);
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}
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/// Construct a ModR/M byte using direct r/m addressing
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/// r/m effective address: r/m
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///
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/// Note reg's effective address is always just reg for the ModR/M byte.
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/// Remember to add a REX prefix byte if reg or rm are extended!
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pub fn modRm_direct(self: Self, reg_or_opx: u3, rm: u3) void {
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self.modRm(0b11, reg_or_opx, rm);
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}
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/// Construct a ModR/M byte using indirect r/m addressing
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/// r/m effective address: [r/m]
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///
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/// Note reg's effective address is always just reg for the ModR/M byte.
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/// Remember to add a REX prefix byte if reg or rm are extended!
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pub fn modRm_indirectDisp0(self: Self, reg_or_opx: u3, rm: u3) void {
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assert(rm != 4 and rm != 5);
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self.modRm(0b00, reg_or_opx, rm);
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}
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/// Construct a ModR/M byte using indirect SIB addressing
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/// r/m effective address: [SIB]
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///
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/// Note reg's effective address is always just reg for the ModR/M byte.
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/// Remember to add a REX prefix byte if reg or rm are extended!
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pub fn modRm_SIBDisp0(self: Self, reg_or_opx: u3) void {
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self.modRm(0b00, reg_or_opx, 0b100);
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}
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/// Construct a ModR/M byte using RIP-relative addressing
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/// r/m effective address: [RIP + disp32]
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///
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/// Note reg's effective address is always just reg for the ModR/M byte.
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/// Remember to add a REX prefix byte if reg or rm are extended!
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pub fn modRm_RIPDisp32(self: Self, reg_or_opx: u3) void {
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self.modRm(0b00, reg_or_opx, 0b101);
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}
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/// Construct a ModR/M byte using indirect r/m with a 8bit displacement
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/// r/m effective address: [r/m + disp8]
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///
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/// Note reg's effective address is always just reg for the ModR/M byte.
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/// Remember to add a REX prefix byte if reg or rm are extended!
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pub fn modRm_indirectDisp8(self: Self, reg_or_opx: u3, rm: u3) void {
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assert(rm != 4);
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self.modRm(0b01, reg_or_opx, rm);
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}
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/// Construct a ModR/M byte using indirect SIB with a 8bit displacement
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/// r/m effective address: [SIB + disp8]
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///
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/// Note reg's effective address is always just reg for the ModR/M byte.
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/// Remember to add a REX prefix byte if reg or rm are extended!
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pub fn modRm_SIBDisp8(self: Self, reg_or_opx: u3) void {
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self.modRm(0b01, reg_or_opx, 0b100);
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}
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/// Construct a ModR/M byte using indirect r/m with a 32bit displacement
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/// r/m effective address: [r/m + disp32]
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///
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/// Note reg's effective address is always just reg for the ModR/M byte.
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/// Remember to add a REX prefix byte if reg or rm are extended!
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pub fn modRm_indirectDisp32(self: Self, reg_or_opx: u3, rm: u3) void {
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assert(rm != 4);
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self.modRm(0b10, reg_or_opx, rm);
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}
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/// Construct a ModR/M byte using indirect SIB with a 32bit displacement
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/// r/m effective address: [SIB + disp32]
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///
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/// Note reg's effective address is always just reg for the ModR/M byte.
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/// Remember to add a REX prefix byte if reg or rm are extended!
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pub fn modRm_SIBDisp32(self: Self, reg_or_opx: u3) void {
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self.modRm(0b10, reg_or_opx, 0b100);
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}
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// ---
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// SIB
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// ---
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/// Construct a SIB byte given all the fields
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///
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/// Remember to add a REX prefix byte if index or base are extended!
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pub fn sib(self: Self, scale: u2, index: u3, base: u3) void {
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self.code.appendAssumeCapacity(
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@as(u8, scale) << 6 | @as(u8, index) << 3 | base,
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);
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}
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/// Construct a SIB byte with scale * index + base, no frills.
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/// r/m effective address: [base + scale * index]
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///
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/// Remember to add a REX prefix byte if index or base are extended!
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pub fn sib_scaleIndexBase(self: Self, scale: u2, index: u3, base: u3) void {
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assert(base != 5);
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self.sib(scale, index, base);
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}
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/// Construct a SIB byte with scale * index + disp32
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/// r/m effective address: [scale * index + disp32]
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///
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/// Remember to add a REX prefix byte if index or base are extended!
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pub fn sib_scaleIndexDisp32(self: Self, scale: u2, index: u3) void {
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assert(index != 4);
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// scale is actually ignored
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// index = 4 means no index
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// base = 5 means no base, if mod == 0.
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self.sib(scale, index, 5);
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}
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/// Construct a SIB byte with just base
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/// r/m effective address: [base]
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///
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/// Remember to add a REX prefix byte if index or base are extended!
|
|
pub fn sib_base(self: Self, base: u3) void {
|
|
assert(base != 5);
|
|
|
|
// scale is actually ignored
|
|
// index = 4 means no index
|
|
self.sib(0, 4, base);
|
|
}
|
|
|
|
/// Construct a SIB byte with just disp32
|
|
/// r/m effective address: [disp32]
|
|
///
|
|
/// Remember to add a REX prefix byte if index or base are extended!
|
|
pub fn sib_disp32(self: Self) void {
|
|
// scale is actually ignored
|
|
// index = 4 means no index
|
|
// base = 5 means no base, if mod == 0.
|
|
self.sib(0, 4, 5);
|
|
}
|
|
|
|
/// Construct a SIB byte with scale * index + base + disp8
|
|
/// r/m effective address: [base + scale * index + disp8]
|
|
///
|
|
/// Remember to add a REX prefix byte if index or base are extended!
|
|
pub fn sib_scaleIndexBaseDisp8(self: Self, scale: u2, index: u3, base: u3) void {
|
|
self.sib(scale, index, base);
|
|
}
|
|
|
|
/// Construct a SIB byte with base + disp8, no index
|
|
/// r/m effective address: [base + disp8]
|
|
///
|
|
/// Remember to add a REX prefix byte if index or base are extended!
|
|
pub fn sib_baseDisp8(self: Self, base: u3) void {
|
|
// scale is ignored
|
|
// index = 4 means no index
|
|
self.sib(0, 4, base);
|
|
}
|
|
|
|
/// Construct a SIB byte with scale * index + base + disp32
|
|
/// r/m effective address: [base + scale * index + disp32]
|
|
///
|
|
/// Remember to add a REX prefix byte if index or base are extended!
|
|
pub fn sib_scaleIndexBaseDisp32(self: Self, scale: u2, index: u3, base: u3) void {
|
|
self.sib(scale, index, base);
|
|
}
|
|
|
|
/// Construct a SIB byte with base + disp32, no index
|
|
/// r/m effective address: [base + disp32]
|
|
///
|
|
/// Remember to add a REX prefix byte if index or base are extended!
|
|
pub fn sib_baseDisp32(self: Self, base: u3) void {
|
|
// scale is ignored
|
|
// index = 4 means no index
|
|
self.sib(0, 4, base);
|
|
}
|
|
|
|
// -------------------------
|
|
// Trivial (no bit fiddling)
|
|
// -------------------------
|
|
|
|
/// Encode an 8 bit immediate
|
|
///
|
|
/// It is sign-extended to 64 bits by the cpu.
|
|
pub fn imm8(self: Self, imm: i8) void {
|
|
self.code.appendAssumeCapacity(@bitCast(u8, imm));
|
|
}
|
|
|
|
/// Encode an 8 bit displacement
|
|
///
|
|
/// It is sign-extended to 64 bits by the cpu.
|
|
pub fn disp8(self: Self, disp: i8) void {
|
|
self.code.appendAssumeCapacity(@bitCast(u8, disp));
|
|
}
|
|
|
|
/// Encode an 16 bit immediate
|
|
///
|
|
/// It is sign-extended to 64 bits by the cpu.
|
|
pub fn imm16(self: Self, imm: i16) void {
|
|
self.writeIntLittle(i16, imm);
|
|
}
|
|
|
|
/// Encode an 32 bit immediate
|
|
///
|
|
/// It is sign-extended to 64 bits by the cpu.
|
|
pub fn imm32(self: Self, imm: i32) void {
|
|
self.writeIntLittle(i32, imm);
|
|
}
|
|
|
|
/// Encode an 32 bit displacement
|
|
///
|
|
/// It is sign-extended to 64 bits by the cpu.
|
|
pub fn disp32(self: Self, disp: i32) void {
|
|
self.writeIntLittle(i32, disp);
|
|
}
|
|
|
|
/// Encode an 64 bit immediate
|
|
///
|
|
/// It is sign-extended to 64 bits by the cpu.
|
|
pub fn imm64(self: Self, imm: u64) void {
|
|
self.writeIntLittle(u64, imm);
|
|
}
|
|
};
|
|
|
|
test "x86_64 Encoder helpers" {
|
|
var code = ArrayList(u8).init(testing.allocator);
|
|
defer code.deinit();
|
|
|
|
// simple integer multiplication
|
|
|
|
// imul eax,edi
|
|
// 0faf c7
|
|
{
|
|
try code.resize(0);
|
|
const encoder = try Encoder.init(&code, 4);
|
|
encoder.rex(.{
|
|
.r = Register.eax.isExtended(),
|
|
.b = Register.edi.isExtended(),
|
|
});
|
|
encoder.opcode_2byte(0x0f, 0xaf);
|
|
encoder.modRm_direct(
|
|
Register.eax.low_id(),
|
|
Register.edi.low_id(),
|
|
);
|
|
|
|
try testing.expectEqualSlices(u8, &[_]u8{ 0x0f, 0xaf, 0xc7 }, code.items);
|
|
}
|
|
|
|
// simple mov
|
|
|
|
// mov eax,edi
|
|
// 89 f8
|
|
{
|
|
try code.resize(0);
|
|
const encoder = try Encoder.init(&code, 3);
|
|
encoder.rex(.{
|
|
.r = Register.edi.isExtended(),
|
|
.b = Register.eax.isExtended(),
|
|
});
|
|
encoder.opcode_1byte(0x89);
|
|
encoder.modRm_direct(
|
|
Register.edi.low_id(),
|
|
Register.eax.low_id(),
|
|
);
|
|
|
|
try testing.expectEqualSlices(u8, &[_]u8{ 0x89, 0xf8 }, code.items);
|
|
}
|
|
|
|
// signed integer addition of 32-bit sign extended immediate to 64 bit register
|
|
|
|
// add rcx, 2147483647
|
|
//
|
|
// Using the following opcode: REX.W + 81 /0 id, we expect the following encoding
|
|
//
|
|
// 48 : REX.W set for 64 bit operand (*r*cx)
|
|
// 81 : opcode for "<arithmetic> with immediate"
|
|
// c1 : id = rcx,
|
|
// : c1 = 11 <-- mod = 11 indicates r/m is register (rcx)
|
|
// : 000 <-- opcode_extension = 0 because opcode extension is /0. /0 specifies ADD
|
|
// : 001 <-- 001 is rcx
|
|
// ffffff7f : 2147483647
|
|
{
|
|
try code.resize(0);
|
|
const encoder = try Encoder.init(&code, 7);
|
|
encoder.rex(.{ .w = true }); // use 64 bit operation
|
|
encoder.opcode_1byte(0x81);
|
|
encoder.modRm_direct(
|
|
0,
|
|
Register.rcx.low_id(),
|
|
);
|
|
encoder.imm32(2147483647);
|
|
|
|
try testing.expectEqualSlices(u8, &[_]u8{ 0x48, 0x81, 0xc1, 0xff, 0xff, 0xff, 0x7f }, code.items);
|
|
}
|
|
}
|
|
|
|
// TODO add these registers to the enum and populate dwarfLocOp
|
|
// // Return Address register. This is stored in `0(%rsp, "")` and is not a physical register.
|
|
// RA = (16, "RA"),
|
|
//
|
|
// XMM0 = (17, "xmm0"),
|
|
// XMM1 = (18, "xmm1"),
|
|
// XMM2 = (19, "xmm2"),
|
|
// XMM3 = (20, "xmm3"),
|
|
// XMM4 = (21, "xmm4"),
|
|
// XMM5 = (22, "xmm5"),
|
|
// XMM6 = (23, "xmm6"),
|
|
// XMM7 = (24, "xmm7"),
|
|
//
|
|
// XMM8 = (25, "xmm8"),
|
|
// XMM9 = (26, "xmm9"),
|
|
// XMM10 = (27, "xmm10"),
|
|
// XMM11 = (28, "xmm11"),
|
|
// XMM12 = (29, "xmm12"),
|
|
// XMM13 = (30, "xmm13"),
|
|
// XMM14 = (31, "xmm14"),
|
|
// XMM15 = (32, "xmm15"),
|
|
//
|
|
// ST0 = (33, "st0"),
|
|
// ST1 = (34, "st1"),
|
|
// ST2 = (35, "st2"),
|
|
// ST3 = (36, "st3"),
|
|
// ST4 = (37, "st4"),
|
|
// ST5 = (38, "st5"),
|
|
// ST6 = (39, "st6"),
|
|
// ST7 = (40, "st7"),
|
|
//
|
|
// MM0 = (41, "mm0"),
|
|
// MM1 = (42, "mm1"),
|
|
// MM2 = (43, "mm2"),
|
|
// MM3 = (44, "mm3"),
|
|
// MM4 = (45, "mm4"),
|
|
// MM5 = (46, "mm5"),
|
|
// MM6 = (47, "mm6"),
|
|
// MM7 = (48, "mm7"),
|
|
//
|
|
// RFLAGS = (49, "rFLAGS"),
|
|
// ES = (50, "es"),
|
|
// CS = (51, "cs"),
|
|
// SS = (52, "ss"),
|
|
// DS = (53, "ds"),
|
|
// FS = (54, "fs"),
|
|
// GS = (55, "gs"),
|
|
//
|
|
// FS_BASE = (58, "fs.base"),
|
|
// GS_BASE = (59, "gs.base"),
|
|
//
|
|
// TR = (62, "tr"),
|
|
// LDTR = (63, "ldtr"),
|
|
// MXCSR = (64, "mxcsr"),
|
|
// FCW = (65, "fcw"),
|
|
// FSW = (66, "fsw"),
|
|
//
|
|
// XMM16 = (67, "xmm16"),
|
|
// XMM17 = (68, "xmm17"),
|
|
// XMM18 = (69, "xmm18"),
|
|
// XMM19 = (70, "xmm19"),
|
|
// XMM20 = (71, "xmm20"),
|
|
// XMM21 = (72, "xmm21"),
|
|
// XMM22 = (73, "xmm22"),
|
|
// XMM23 = (74, "xmm23"),
|
|
// XMM24 = (75, "xmm24"),
|
|
// XMM25 = (76, "xmm25"),
|
|
// XMM26 = (77, "xmm26"),
|
|
// XMM27 = (78, "xmm27"),
|
|
// XMM28 = (79, "xmm28"),
|
|
// XMM29 = (80, "xmm29"),
|
|
// XMM30 = (81, "xmm30"),
|
|
// XMM31 = (82, "xmm31"),
|
|
//
|
|
// K0 = (118, "k0"),
|
|
// K1 = (119, "k1"),
|
|
// K2 = (120, "k2"),
|
|
// K3 = (121, "k3"),
|
|
// K4 = (122, "k4"),
|
|
// K5 = (123, "k5"),
|
|
// K6 = (124, "k6"),
|
|
// K7 = (125, "k7"),
|