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aa92446365
In codegen.zig, the std.Target.Cpu.Arch is now generally available as a comptime value where needed. This is a tradeoff that causes the compiler binary to be more bloated, but gives us higher performance, since the optimizer can optimize per architecture (which is usually how compilers are designed anyway, with different code per-architecture), and it also allows us to use per-architecture types, such as a Register enum that is specific to the comptime-known architecture. Adds abiSize method to Type.
92 lines
3.5 KiB
Zig
92 lines
3.5 KiB
Zig
const Type = @import("../Type.zig");
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// zig fmt: off
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/// Definitions of all of the x64 registers. The order is semantically meaningful.
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/// The registers are defined such that IDs go in descending order of 64-bit,
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/// 32-bit, 16-bit, and then 8-bit, and each set contains exactly sixteen
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/// registers. This results in some useful properties:
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///
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/// Any 64-bit register can be turned into its 32-bit form by adding 16, and
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/// vice versa. This also works between 32-bit and 16-bit forms. With 8-bit, it
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/// works for all except for sp, bp, si, and di, which do *not* have an 8-bit
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/// form.
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///
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/// If (register & 8) is set, the register is extended.
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///
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/// The ID can be easily determined by figuring out what range the register is
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/// in, and then subtracting the base.
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pub const Register = enum(u8) {
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// 0 through 15, 64-bit registers. 8-15 are extended.
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// id is just the int value.
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rax, rcx, rdx, rbx, rsp, rbp, rsi, rdi,
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r8, r9, r10, r11, r12, r13, r14, r15,
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// 16 through 31, 32-bit registers. 24-31 are extended.
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// id is int value - 16.
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eax, ecx, edx, ebx, esp, ebp, esi, edi,
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r8d, r9d, r10d, r11d, r12d, r13d, r14d, r15d,
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// 32-47, 16-bit registers. 40-47 are extended.
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// id is int value - 32.
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ax, cx, dx, bx, sp, bp, si, di,
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r8w, r9w, r10w, r11w, r12w, r13w, r14w, r15w,
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// 48-63, 8-bit registers. 56-63 are extended.
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// id is int value - 48.
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al, cl, dl, bl, ah, ch, dh, bh,
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r8b, r9b, r10b, r11b, r12b, r13b, r14b, r15b,
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/// Returns the bit-width of the register.
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pub fn size(self: @This()) u7 {
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return switch (@enumToInt(self)) {
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0...15 => 64,
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16...31 => 32,
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32...47 => 16,
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48...64 => 8,
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else => unreachable,
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};
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}
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/// Returns whether the register is *extended*. Extended registers are the
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/// new registers added with amd64, r8 through r15. This also includes any
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/// other variant of access to those registers, such as r8b, r15d, and so
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/// on. This is needed because access to these registers requires special
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/// handling via the REX prefix, via the B or R bits, depending on context.
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pub fn isExtended(self: @This()) bool {
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return @enumToInt(self) & 0x08 != 0;
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}
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/// This returns the 4-bit register ID, which is used in practically every
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/// opcode. Note that bit 3 (the highest bit) is *never* used directly in
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/// an instruction (@see isExtended), and requires special handling. The
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/// lower three bits are often embedded directly in instructions (such as
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/// the B8 variant of moves), or used in R/M bytes.
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pub fn id(self: @This()) u4 {
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return @truncate(u4, @enumToInt(self));
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}
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};
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// zig fmt: on
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/// After argument values have been computed, they are placed either in registers
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/// or pushed on the stack. The way values are passed depends on the class.
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pub const ParameterClass = enum {
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/// Integral types that fit into one of the general purpose registers.
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integer,
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/// Types that fit into a vector register.
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sse,
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/// Types that fit into a vector register and can be passed
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/// and returned in the upper bytes of it.
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sse_up,
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/// Types that will be returned via the x87FPU.
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x87,
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/// Types that will be returned via the x87FPU and can be passed and returned
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/// in the upper bytes of it.
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x87_up,
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/// Types that will be returned via the x87FPU.
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complex_x87,
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/// Types that will be passed and returned in mem-ory via the stack.
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memory,
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};
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