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zig/lib/std/target/feature/AArch64Feature.zig
Layne Gustafson 0f46c12f78
Create initial target details infrastructure
2020-01-19 20:53:15 -05:00

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const FeatureInfo = @import("std").target.feature.FeatureInfo;
pub const AArch64Feature = enum {
Aes,
Am,
AggressiveFma,
Altnzcv,
AlternateSextloadCvtF32Pattern,
ArithBccFusion,
ArithCbzFusion,
BalanceFpOps,
Bti,
Ccidx,
Ccpp,
Crc,
Ccdp,
CallSavedX8,
CallSavedX9,
CallSavedX10,
CallSavedX11,
CallSavedX12,
CallSavedX13,
CallSavedX14,
CallSavedX15,
CallSavedX18,
Complxnum,
Crypto,
CustomCheapAsMove,
Dit,
DisableLatencySchedHeuristic,
Dotprod,
Ete,
ExynosCheapAsMove,
Fmi,
Fp16fml,
FpArmv8,
Fptoint,
Force32bitJumpTables,
Fullfp16,
FuseAes,
FuseAddress,
FuseArithLogic,
FuseCsel,
FuseCryptoEor,
FuseLiterals,
Jsconv,
Lor,
Lse,
LslFast,
Mpam,
Mte,
Neon,
Nv,
NoNegImmediates,
Pa,
Pan,
PanRwv,
Perfmon,
UsePostraScheduler,
Predres,
PredictableSelectExpensive,
Uaops,
Ras,
Rasv8_4,
Rcpc,
RcpcImmo,
Rdm,
Rand,
ReserveX1,
ReserveX2,
ReserveX3,
ReserveX4,
ReserveX5,
ReserveX6,
ReserveX7,
ReserveX9,
ReserveX10,
ReserveX11,
ReserveX12,
ReserveX13,
ReserveX14,
ReserveX15,
ReserveX18,
ReserveX20,
ReserveX21,
ReserveX22,
ReserveX23,
ReserveX24,
ReserveX25,
ReserveX26,
ReserveX27,
ReserveX28,
Sb,
Sel2,
Sha2,
Sha3,
Sm4,
Spe,
Ssbs,
Sve,
Sve2,
Sve2Aes,
Sve2Bitperm,
Sve2Sha3,
Sve2Sm4,
SlowMisaligned128store,
SlowPaired128,
SlowStrqroStore,
Specrestrict,
StrictAlign,
TlbRmi,
Tme,
Tracev84,
Trbe,
TaggedGlobals,
UseAa,
TpidrEl1,
TpidrEl2,
TpidrEl3,
UseReciprocalSquareRoot,
Vh,
Zcm,
Zcz,
ZczFp,
ZczFpWorkaround,
ZczGp,
V81a,
V82a,
V83a,
V84a,
V85a,
A35,
A53,
A55,
A57,
A65,
A72,
A73,
A75,
A76,
Cyclone,
Exynosm1,
Exynosm2,
Exynosm3,
Exynosm4,
Falkor,
Kryo,
Neoversee1,
Neoversen1,
Saphira,
Tsv110,
Thunderx,
Thunderx2t99,
Thunderxt81,
Thunderxt83,
Thunderxt88,
pub fn getInfo(self: @This()) FeatureInfo {
return feature_infos[@enumToInt(self)];
}
pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
FeatureInfo(@This()).createWithSubfeatures(.Aes, "aes", "Enable AES support", "aes", &[_]@This() {
.FpArmv8,
}),
FeatureInfo(@This()).create(.Am, "am", "Enable v8.4-A Activity Monitors extension", "am"),
FeatureInfo(@This()).create(.AggressiveFma, "aggressive-fma", "Enable Aggressive FMA for floating-point.", "aggressive-fma"),
FeatureInfo(@This()).create(.Altnzcv, "altnzcv", "Enable alternative NZCV format for floating point comparisons", "altnzcv"),
FeatureInfo(@This()).create(.AlternateSextloadCvtF32Pattern, "alternate-sextload-cvt-f32-pattern", "Use alternative pattern for sextload convert to f32", "alternate-sextload-cvt-f32-pattern"),
FeatureInfo(@This()).create(.ArithBccFusion, "arith-bcc-fusion", "CPU fuses arithmetic+bcc operations", "arith-bcc-fusion"),
FeatureInfo(@This()).create(.ArithCbzFusion, "arith-cbz-fusion", "CPU fuses arithmetic + cbz/cbnz operations", "arith-cbz-fusion"),
FeatureInfo(@This()).create(.BalanceFpOps, "balance-fp-ops", "balance mix of odd and even D-registers for fp multiply(-accumulate) ops", "balance-fp-ops"),
FeatureInfo(@This()).create(.Bti, "bti", "Enable Branch Target Identification", "bti"),
FeatureInfo(@This()).create(.Ccidx, "ccidx", "Enable v8.3-A Extend of the CCSIDR number of sets", "ccidx"),
FeatureInfo(@This()).create(.Ccpp, "ccpp", "Enable v8.2 data Cache Clean to Point of Persistence", "ccpp"),
FeatureInfo(@This()).create(.Crc, "crc", "Enable ARMv8 CRC-32 checksum instructions", "crc"),
FeatureInfo(@This()).create(.Ccdp, "ccdp", "Enable v8.5 Cache Clean to Point of Deep Persistence", "ccdp"),
FeatureInfo(@This()).create(.CallSavedX8, "call-saved-x8", "Make X8 callee saved.", "call-saved-x8"),
FeatureInfo(@This()).create(.CallSavedX9, "call-saved-x9", "Make X9 callee saved.", "call-saved-x9"),
FeatureInfo(@This()).create(.CallSavedX10, "call-saved-x10", "Make X10 callee saved.", "call-saved-x10"),
FeatureInfo(@This()).create(.CallSavedX11, "call-saved-x11", "Make X11 callee saved.", "call-saved-x11"),
FeatureInfo(@This()).create(.CallSavedX12, "call-saved-x12", "Make X12 callee saved.", "call-saved-x12"),
FeatureInfo(@This()).create(.CallSavedX13, "call-saved-x13", "Make X13 callee saved.", "call-saved-x13"),
FeatureInfo(@This()).create(.CallSavedX14, "call-saved-x14", "Make X14 callee saved.", "call-saved-x14"),
FeatureInfo(@This()).create(.CallSavedX15, "call-saved-x15", "Make X15 callee saved.", "call-saved-x15"),
FeatureInfo(@This()).create(.CallSavedX18, "call-saved-x18", "Make X18 callee saved.", "call-saved-x18"),
FeatureInfo(@This()).createWithSubfeatures(.Complxnum, "complxnum", "Enable v8.3-A Floating-point complex number support", "complxnum", &[_]@This() {
.FpArmv8,
}),
FeatureInfo(@This()).createWithSubfeatures(.Crypto, "crypto", "Enable cryptographic instructions", "crypto", &[_]@This() {
.FpArmv8,
}),
FeatureInfo(@This()).create(.CustomCheapAsMove, "custom-cheap-as-move", "Use custom handling of cheap instructions", "custom-cheap-as-move"),
FeatureInfo(@This()).create(.Dit, "dit", "Enable v8.4-A Data Independent Timing instructions", "dit"),
FeatureInfo(@This()).create(.DisableLatencySchedHeuristic, "disable-latency-sched-heuristic", "Disable latency scheduling heuristic", "disable-latency-sched-heuristic"),
FeatureInfo(@This()).create(.Dotprod, "dotprod", "Enable dot product support", "dotprod"),
FeatureInfo(@This()).createWithSubfeatures(.Ete, "ete", "Enable Embedded Trace Extension", "ete", &[_]@This() {
.Trbe,
}),
FeatureInfo(@This()).createWithSubfeatures(.ExynosCheapAsMove, "exynos-cheap-as-move", "Use Exynos specific handling of cheap instructions", "exynos-cheap-as-move", &[_]@This() {
.CustomCheapAsMove,
}),
FeatureInfo(@This()).create(.Fmi, "fmi", "Enable v8.4-A Flag Manipulation Instructions", "fmi"),
FeatureInfo(@This()).createWithSubfeatures(.Fp16fml, "fp16fml", "Enable FP16 FML instructions", "fp16fml", &[_]@This() {
.FpArmv8,
}),
FeatureInfo(@This()).create(.FpArmv8, "fp-armv8", "Enable ARMv8 FP", "fp-armv8"),
FeatureInfo(@This()).create(.Fptoint, "fptoint", "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int", "fptoint"),
FeatureInfo(@This()).create(.Force32bitJumpTables, "force-32bit-jump-tables", "Force jump table entries to be 32-bits wide except at MinSize", "force-32bit-jump-tables"),
FeatureInfo(@This()).createWithSubfeatures(.Fullfp16, "fullfp16", "Full FP16", "fullfp16", &[_]@This() {
.FpArmv8,
}),
FeatureInfo(@This()).create(.FuseAes, "fuse-aes", "CPU fuses AES crypto operations", "fuse-aes"),
FeatureInfo(@This()).create(.FuseAddress, "fuse-address", "CPU fuses address generation and memory operations", "fuse-address"),
FeatureInfo(@This()).create(.FuseArithLogic, "fuse-arith-logic", "CPU fuses arithmetic and logic operations", "fuse-arith-logic"),
FeatureInfo(@This()).create(.FuseCsel, "fuse-csel", "CPU fuses conditional select operations", "fuse-csel"),
FeatureInfo(@This()).create(.FuseCryptoEor, "fuse-crypto-eor", "CPU fuses AES/PMULL and EOR operations", "fuse-crypto-eor"),
FeatureInfo(@This()).create(.FuseLiterals, "fuse-literals", "CPU fuses literal generation operations", "fuse-literals"),
FeatureInfo(@This()).createWithSubfeatures(.Jsconv, "jsconv", "Enable v8.3-A JavaScript FP conversion enchancement", "jsconv", &[_]@This() {
.FpArmv8,
}),
FeatureInfo(@This()).create(.Lor, "lor", "Enables ARM v8.1 Limited Ordering Regions extension", "lor"),
FeatureInfo(@This()).create(.Lse, "lse", "Enable ARMv8.1 Large System Extension (LSE) atomic instructions", "lse"),
FeatureInfo(@This()).create(.LslFast, "lsl-fast", "CPU has a fastpath logical shift of up to 3 places", "lsl-fast"),
FeatureInfo(@This()).create(.Mpam, "mpam", "Enable v8.4-A Memory system Partitioning and Monitoring extension", "mpam"),
FeatureInfo(@This()).create(.Mte, "mte", "Enable Memory Tagging Extension", "mte"),
FeatureInfo(@This()).createWithSubfeatures(.Neon, "neon", "Enable Advanced SIMD instructions", "neon", &[_]@This() {
.FpArmv8,
}),
FeatureInfo(@This()).create(.Nv, "nv", "Enable v8.4-A Nested Virtualization Enchancement", "nv"),
FeatureInfo(@This()).create(.NoNegImmediates, "no-neg-immediates", "Convert immediates and instructions to their negated or complemented equivalent when the immediate does not fit in the encoding.", "no-neg-immediates"),
FeatureInfo(@This()).create(.Pa, "pa", "Enable v8.3-A Pointer Authentication enchancement", "pa"),
FeatureInfo(@This()).create(.Pan, "pan", "Enables ARM v8.1 Privileged Access-Never extension", "pan"),
FeatureInfo(@This()).createWithSubfeatures(.PanRwv, "pan-rwv", "Enable v8.2 PAN s1e1R and s1e1W Variants", "pan-rwv", &[_]@This() {
.Pan,
}),
FeatureInfo(@This()).create(.Perfmon, "perfmon", "Enable ARMv8 PMUv3 Performance Monitors extension", "perfmon"),
FeatureInfo(@This()).create(.UsePostraScheduler, "use-postra-scheduler", "Schedule again after register allocation", "use-postra-scheduler"),
FeatureInfo(@This()).create(.Predres, "predres", "Enable v8.5a execution and data prediction invalidation instructions", "predres"),
FeatureInfo(@This()).create(.PredictableSelectExpensive, "predictable-select-expensive", "Prefer likely predicted branches over selects", "predictable-select-expensive"),
FeatureInfo(@This()).create(.Uaops, "uaops", "Enable v8.2 UAO PState", "uaops"),
FeatureInfo(@This()).create(.Ras, "ras", "Enable ARMv8 Reliability, Availability and Serviceability Extensions", "ras"),
FeatureInfo(@This()).createWithSubfeatures(.Rasv8_4, "rasv8_4", "Enable v8.4-A Reliability, Availability and Serviceability extension", "rasv8_4", &[_]@This() {
.Ras,
}),
FeatureInfo(@This()).create(.Rcpc, "rcpc", "Enable support for RCPC extension", "rcpc"),
FeatureInfo(@This()).createWithSubfeatures(.RcpcImmo, "rcpc-immo", "Enable v8.4-A RCPC instructions with Immediate Offsets", "rcpc-immo", &[_]@This() {
.Rcpc,
}),
FeatureInfo(@This()).create(.Rdm, "rdm", "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions", "rdm"),
FeatureInfo(@This()).create(.Rand, "rand", "Enable Random Number generation instructions", "rand"),
FeatureInfo(@This()).create(.ReserveX1, "reserve-x1", "Reserve X1, making it unavailable as a GPR", "reserve-x1"),
FeatureInfo(@This()).create(.ReserveX2, "reserve-x2", "Reserve X2, making it unavailable as a GPR", "reserve-x2"),
FeatureInfo(@This()).create(.ReserveX3, "reserve-x3", "Reserve X3, making it unavailable as a GPR", "reserve-x3"),
FeatureInfo(@This()).create(.ReserveX4, "reserve-x4", "Reserve X4, making it unavailable as a GPR", "reserve-x4"),
FeatureInfo(@This()).create(.ReserveX5, "reserve-x5", "Reserve X5, making it unavailable as a GPR", "reserve-x5"),
FeatureInfo(@This()).create(.ReserveX6, "reserve-x6", "Reserve X6, making it unavailable as a GPR", "reserve-x6"),
FeatureInfo(@This()).create(.ReserveX7, "reserve-x7", "Reserve X7, making it unavailable as a GPR", "reserve-x7"),
FeatureInfo(@This()).create(.ReserveX9, "reserve-x9", "Reserve X9, making it unavailable as a GPR", "reserve-x9"),
FeatureInfo(@This()).create(.ReserveX10, "reserve-x10", "Reserve X10, making it unavailable as a GPR", "reserve-x10"),
FeatureInfo(@This()).create(.ReserveX11, "reserve-x11", "Reserve X11, making it unavailable as a GPR", "reserve-x11"),
FeatureInfo(@This()).create(.ReserveX12, "reserve-x12", "Reserve X12, making it unavailable as a GPR", "reserve-x12"),
FeatureInfo(@This()).create(.ReserveX13, "reserve-x13", "Reserve X13, making it unavailable as a GPR", "reserve-x13"),
FeatureInfo(@This()).create(.ReserveX14, "reserve-x14", "Reserve X14, making it unavailable as a GPR", "reserve-x14"),
FeatureInfo(@This()).create(.ReserveX15, "reserve-x15", "Reserve X15, making it unavailable as a GPR", "reserve-x15"),
FeatureInfo(@This()).create(.ReserveX18, "reserve-x18", "Reserve X18, making it unavailable as a GPR", "reserve-x18"),
FeatureInfo(@This()).create(.ReserveX20, "reserve-x20", "Reserve X20, making it unavailable as a GPR", "reserve-x20"),
FeatureInfo(@This()).create(.ReserveX21, "reserve-x21", "Reserve X21, making it unavailable as a GPR", "reserve-x21"),
FeatureInfo(@This()).create(.ReserveX22, "reserve-x22", "Reserve X22, making it unavailable as a GPR", "reserve-x22"),
FeatureInfo(@This()).create(.ReserveX23, "reserve-x23", "Reserve X23, making it unavailable as a GPR", "reserve-x23"),
FeatureInfo(@This()).create(.ReserveX24, "reserve-x24", "Reserve X24, making it unavailable as a GPR", "reserve-x24"),
FeatureInfo(@This()).create(.ReserveX25, "reserve-x25", "Reserve X25, making it unavailable as a GPR", "reserve-x25"),
FeatureInfo(@This()).create(.ReserveX26, "reserve-x26", "Reserve X26, making it unavailable as a GPR", "reserve-x26"),
FeatureInfo(@This()).create(.ReserveX27, "reserve-x27", "Reserve X27, making it unavailable as a GPR", "reserve-x27"),
FeatureInfo(@This()).create(.ReserveX28, "reserve-x28", "Reserve X28, making it unavailable as a GPR", "reserve-x28"),
FeatureInfo(@This()).create(.Sb, "sb", "Enable v8.5 Speculation Barrier", "sb"),
FeatureInfo(@This()).create(.Sel2, "sel2", "Enable v8.4-A Secure Exception Level 2 extension", "sel2"),
FeatureInfo(@This()).createWithSubfeatures(.Sha2, "sha2", "Enable SHA1 and SHA256 support", "sha2", &[_]@This() {
.FpArmv8,
}),
FeatureInfo(@This()).createWithSubfeatures(.Sha3, "sha3", "Enable SHA512 and SHA3 support", "sha3", &[_]@This() {
.FpArmv8,
}),
FeatureInfo(@This()).createWithSubfeatures(.Sm4, "sm4", "Enable SM3 and SM4 support", "sm4", &[_]@This() {
.FpArmv8,
}),
FeatureInfo(@This()).create(.Spe, "spe", "Enable Statistical Profiling extension", "spe"),
FeatureInfo(@This()).create(.Ssbs, "ssbs", "Enable Speculative Store Bypass Safe bit", "ssbs"),
FeatureInfo(@This()).create(.Sve, "sve", "Enable Scalable Vector Extension (SVE) instructions", "sve"),
FeatureInfo(@This()).createWithSubfeatures(.Sve2, "sve2", "Enable Scalable Vector Extension 2 (SVE2) instructions", "sve2", &[_]@This() {
.Sve,
}),
FeatureInfo(@This()).createWithSubfeatures(.Sve2Aes, "sve2-aes", "Enable AES SVE2 instructions", "sve2-aes", &[_]@This() {
.Sve,
.FpArmv8,
}),
FeatureInfo(@This()).createWithSubfeatures(.Sve2Bitperm, "sve2-bitperm", "Enable bit permutation SVE2 instructions", "sve2-bitperm", &[_]@This() {
.Sve,
}),
FeatureInfo(@This()).createWithSubfeatures(.Sve2Sha3, "sve2-sha3", "Enable SHA3 SVE2 instructions", "sve2-sha3", &[_]@This() {
.Sve,
.FpArmv8,
}),
FeatureInfo(@This()).createWithSubfeatures(.Sve2Sm4, "sve2-sm4", "Enable SM4 SVE2 instructions", "sve2-sm4", &[_]@This() {
.Sve,
.FpArmv8,
}),
FeatureInfo(@This()).create(.SlowMisaligned128store, "slow-misaligned-128store", "Misaligned 128 bit stores are slow", "slow-misaligned-128store"),
FeatureInfo(@This()).create(.SlowPaired128, "slow-paired-128", "Paired 128 bit loads and stores are slow", "slow-paired-128"),
FeatureInfo(@This()).create(.SlowStrqroStore, "slow-strqro-store", "STR of Q register with register offset is slow", "slow-strqro-store"),
FeatureInfo(@This()).create(.Specrestrict, "specrestrict", "Enable architectural speculation restriction", "specrestrict"),
FeatureInfo(@This()).create(.StrictAlign, "strict-align", "Disallow all unaligned memory access", "strict-align"),
FeatureInfo(@This()).create(.TlbRmi, "tlb-rmi", "Enable v8.4-A TLB Range and Maintenance Instructions", "tlb-rmi"),
FeatureInfo(@This()).create(.Tme, "tme", "Enable Transactional Memory Extension", "tme"),
FeatureInfo(@This()).create(.Tracev84, "tracev8.4", "Enable v8.4-A Trace extension", "tracev8.4"),
FeatureInfo(@This()).create(.Trbe, "trbe", "Enable Trace Buffer Extension", "trbe"),
FeatureInfo(@This()).create(.TaggedGlobals, "tagged-globals", "Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits", "tagged-globals"),
FeatureInfo(@This()).create(.UseAa, "use-aa", "Use alias analysis during codegen", "use-aa"),
FeatureInfo(@This()).create(.TpidrEl1, "tpidr-el1", "Permit use of TPIDR_EL1 for the TLS base", "tpidr-el1"),
FeatureInfo(@This()).create(.TpidrEl2, "tpidr-el2", "Permit use of TPIDR_EL2 for the TLS base", "tpidr-el2"),
FeatureInfo(@This()).create(.TpidrEl3, "tpidr-el3", "Permit use of TPIDR_EL3 for the TLS base", "tpidr-el3"),
FeatureInfo(@This()).create(.UseReciprocalSquareRoot, "use-reciprocal-square-root", "Use the reciprocal square root approximation", "use-reciprocal-square-root"),
FeatureInfo(@This()).create(.Vh, "vh", "Enables ARM v8.1 Virtual Host extension", "vh"),
FeatureInfo(@This()).create(.Zcm, "zcm", "Has zero-cycle register moves", "zcm"),
FeatureInfo(@This()).createWithSubfeatures(.Zcz, "zcz", "Has zero-cycle zeroing instructions", "zcz", &[_]@This() {
.ZczFp,
.ZczGp,
}),
FeatureInfo(@This()).create(.ZczFp, "zcz-fp", "Has zero-cycle zeroing instructions for FP registers", "zcz-fp"),
FeatureInfo(@This()).create(.ZczFpWorkaround, "zcz-fp-workaround", "The zero-cycle floating-point zeroing instruction has a bug", "zcz-fp-workaround"),
FeatureInfo(@This()).create(.ZczGp, "zcz-gp", "Has zero-cycle zeroing instructions for generic registers", "zcz-gp"),
FeatureInfo(@This()).createWithSubfeatures(.V81a, "v8.1a", "Support ARM v8.1a instructions", "v8.1a", &[_]@This() {
.Pan,
.Rdm,
.Lse,
.Crc,
.Lor,
.Vh,
}),
FeatureInfo(@This()).createWithSubfeatures(.V82a, "v8.2a", "Support ARM v8.2a instructions", "v8.2a", &[_]@This() {
.Ccpp,
.Pan,
.Rdm,
.Lse,
.Crc,
.Lor,
.Uaops,
.Vh,
.Ras,
}),
FeatureInfo(@This()).createWithSubfeatures(.V83a, "v8.3a", "Support ARM v8.3a instructions", "v8.3a", &[_]@This() {
.Rcpc,
.Ccpp,
.Pan,
.Rdm,
.FpArmv8,
.Lse,
.Ccidx,
.Crc,
.Lor,
.Pa,
.Uaops,
.Vh,
.Ras,
}),
FeatureInfo(@This()).createWithSubfeatures(.V84a, "v8.4a", "Support ARM v8.4a instructions", "v8.4a", &[_]@This() {
.Nv,
.Am,
.Lse,
.Sel2,
.Lor,
.Tracev84,
.Uaops,
.Ccpp,
.TlbRmi,
.Fmi,
.Rcpc,
.Pan,
.Rdm,
.Pa,
.Dit,
.Ras,
.Mpam,
.FpArmv8,
.Ccidx,
.Dotprod,
.Crc,
.Vh,
}),
FeatureInfo(@This()).createWithSubfeatures(.V85a, "v8.5a", "Support ARM v8.5a instructions", "v8.5a", &[_]@This() {
.Nv,
.Am,
.Lse,
.Fptoint,
.Sel2,
.Lor,
.Tracev84,
.Uaops,
.Sb,
.Ccpp,
.Specrestrict,
.Bti,
.Ccdp,
.TlbRmi,
.Fmi,
.Rcpc,
.Pan,
.Rdm,
.Pa,
.Ssbs,
.Dit,
.Ras,
.Mpam,
.Altnzcv,
.FpArmv8,
.Ccidx,
.Dotprod,
.Crc,
.Predres,
.Vh,
}),
FeatureInfo(@This()).createWithSubfeatures(.A35, "a35", "Cortex-A35 ARM processors", "a35", &[_]@This() {
.Perfmon,
.FpArmv8,
.Crc,
}),
FeatureInfo(@This()).createWithSubfeatures(.A53, "a53", "Cortex-A53 ARM processors", "a53", &[_]@This() {
.UseAa,
.FuseAes,
.FpArmv8,
.Perfmon,
.Crc,
.BalanceFpOps,
.UsePostraScheduler,
.CustomCheapAsMove,
}),
FeatureInfo(@This()).createWithSubfeatures(.A55, "a55", "Cortex-A55 ARM processors", "a55", &[_]@This() {
.Rcpc,
.Ccpp,
.Pan,
.Rdm,
.FuseAes,
.Perfmon,
.FpArmv8,
.Lse,
.Crc,
.Dotprod,
.Lor,
.Uaops,
.Vh,
.Ras,
}),
FeatureInfo(@This()).createWithSubfeatures(.A57, "a57", "Cortex-A57 ARM processors", "a57", &[_]@This() {
.FuseLiterals,
.FuseAes,
.FpArmv8,
.Perfmon,
.Crc,
.BalanceFpOps,
.UsePostraScheduler,
.CustomCheapAsMove,
.PredictableSelectExpensive,
}),
FeatureInfo(@This()).createWithSubfeatures(.A65, "a65", "Cortex-A65 ARM processors", "a65", &[_]@This() {
.Rcpc,
.Ccpp,
.Pan,
.Rdm,
.FpArmv8,
.Lse,
.Crc,
.Dotprod,
.Lor,
.Ssbs,
.Uaops,
.Vh,
.Ras,
}),
FeatureInfo(@This()).createWithSubfeatures(.A72, "a72", "Cortex-A72 ARM processors", "a72", &[_]@This() {
.Perfmon,
.FuseAes,
.FpArmv8,
.Crc,
}),
FeatureInfo(@This()).createWithSubfeatures(.A73, "a73", "Cortex-A73 ARM processors", "a73", &[_]@This() {
.Perfmon,
.FuseAes,
.FpArmv8,
.Crc,
}),
FeatureInfo(@This()).createWithSubfeatures(.A75, "a75", "Cortex-A75 ARM processors", "a75", &[_]@This() {
.Rcpc,
.Ccpp,
.Pan,
.Rdm,
.FuseAes,
.Perfmon,
.FpArmv8,
.Lse,
.Crc,
.Dotprod,
.Lor,
.Uaops,
.Vh,
.Ras,
}),
FeatureInfo(@This()).createWithSubfeatures(.A76, "a76", "Cortex-A76 ARM processors", "a76", &[_]@This() {
.Rcpc,
.Ccpp,
.Pan,
.Rdm,
.FpArmv8,
.Lse,
.Crc,
.Dotprod,
.Lor,
.Ssbs,
.Uaops,
.Vh,
.Ras,
}),
FeatureInfo(@This()).createWithSubfeatures(.Cyclone, "cyclone", "Cyclone", "cyclone", &[_]@This() {
.ZczFp,
.ArithCbzFusion,
.FuseAes,
.AlternateSextloadCvtF32Pattern,
.ZczFpWorkaround,
.FpArmv8,
.Perfmon,
.DisableLatencySchedHeuristic,
.Zcm,
.ZczGp,
.ArithBccFusion,
.FuseCryptoEor,
}),
FeatureInfo(@This()).createWithSubfeatures(.Exynosm1, "exynosm1", "Samsung Exynos-M1 processors", "exynosm1", &[_]@This() {
.ZczFp,
.FuseAes,
.SlowPaired128,
.Force32bitJumpTables,
.UseReciprocalSquareRoot,
.FpArmv8,
.Perfmon,
.SlowMisaligned128store,
.Crc,
.UsePostraScheduler,
.CustomCheapAsMove,
}),
FeatureInfo(@This()).createWithSubfeatures(.Exynosm2, "exynosm2", "Samsung Exynos-M2 processors", "exynosm2", &[_]@This() {
.ZczFp,
.FuseAes,
.SlowPaired128,
.Force32bitJumpTables,
.FpArmv8,
.Perfmon,
.SlowMisaligned128store,
.Crc,
.UsePostraScheduler,
.CustomCheapAsMove,
}),
FeatureInfo(@This()).createWithSubfeatures(.Exynosm3, "exynosm3", "Samsung Exynos-M3 processors", "exynosm3", &[_]@This() {
.ZczFp,
.FuseLiterals,
.FuseAes,
.Force32bitJumpTables,
.FpArmv8,
.Perfmon,
.Crc,
.LslFast,
.FuseAddress,
.UsePostraScheduler,
.CustomCheapAsMove,
.PredictableSelectExpensive,
.FuseCsel,
}),
FeatureInfo(@This()).createWithSubfeatures(.Exynosm4, "exynosm4", "Samsung Exynos-M4 processors", "exynosm4", &[_]@This() {
.ZczFp,
.Lse,
.FuseArithLogic,
.Lor,
.UsePostraScheduler,
.Uaops,
.CustomCheapAsMove,
.ArithBccFusion,
.Ccpp,
.Perfmon,
.Pan,
.Rdm,
.FuseLiterals,
.Force32bitJumpTables,
.LslFast,
.FuseAddress,
.ZczGp,
.Ras,
.FuseCsel,
.ArithCbzFusion,
.FuseAes,
.FpArmv8,
.Crc,
.Dotprod,
.Vh,
}),
FeatureInfo(@This()).createWithSubfeatures(.Falkor, "falkor", "Qualcomm Falkor processors", "falkor", &[_]@This() {
.ZczFp,
.Rdm,
.SlowStrqroStore,
.Perfmon,
.FpArmv8,
.Crc,
.LslFast,
.UsePostraScheduler,
.ZczGp,
.CustomCheapAsMove,
.PredictableSelectExpensive,
}),
FeatureInfo(@This()).createWithSubfeatures(.Kryo, "kryo", "Qualcomm Kryo processors", "kryo", &[_]@This() {
.ZczFp,
.Perfmon,
.FpArmv8,
.Crc,
.LslFast,
.UsePostraScheduler,
.ZczGp,
.CustomCheapAsMove,
.PredictableSelectExpensive,
}),
FeatureInfo(@This()).createWithSubfeatures(.Neoversee1, "neoversee1", "Neoverse E1 ARM processors", "neoversee1", &[_]@This() {
.Rcpc,
.Ccpp,
.Pan,
.Rdm,
.FpArmv8,
.Lse,
.Crc,
.Dotprod,
.Lor,
.Ssbs,
.Uaops,
.Vh,
.Ras,
}),
FeatureInfo(@This()).createWithSubfeatures(.Neoversen1, "neoversen1", "Neoverse N1 ARM processors", "neoversen1", &[_]@This() {
.Rcpc,
.Spe,
.Ccpp,
.Pan,
.Rdm,
.FpArmv8,
.Lse,
.Crc,
.Dotprod,
.Lor,
.Ssbs,
.Uaops,
.Vh,
.Ras,
}),
FeatureInfo(@This()).createWithSubfeatures(.Saphira, "saphira", "Qualcomm Saphira processors", "saphira", &[_]@This() {
.ZczFp,
.Nv,
.Am,
.Lse,
.Sel2,
.Lor,
.Tracev84,
.Uaops,
.UsePostraScheduler,
.CustomCheapAsMove,
.Ccpp,
.Perfmon,
.TlbRmi,
.PredictableSelectExpensive,
.Fmi,
.Rcpc,
.Pan,
.Rdm,
.LslFast,
.Pa,
.ZczGp,
.Dit,
.Ras,
.Spe,
.Mpam,
.FpArmv8,
.Ccidx,
.Dotprod,
.Crc,
.Vh,
}),
FeatureInfo(@This()).createWithSubfeatures(.Tsv110, "tsv110", "HiSilicon TS-V110 processors", "tsv110", &[_]@This() {
.Uaops,
.Spe,
.Ccpp,
.Pan,
.Rdm,
.FuseAes,
.Vh,
.Perfmon,
.FpArmv8,
.Lse,
.Crc,
.Dotprod,
.Lor,
.UsePostraScheduler,
.CustomCheapAsMove,
.Ras,
}),
FeatureInfo(@This()).createWithSubfeatures(.Thunderx, "thunderx", "Cavium ThunderX processors", "thunderx", &[_]@This() {
.Perfmon,
.FpArmv8,
.Crc,
.UsePostraScheduler,
.PredictableSelectExpensive,
}),
FeatureInfo(@This()).createWithSubfeatures(.Thunderx2t99, "thunderx2t99", "Cavium ThunderX2 processors", "thunderx2t99", &[_]@This() {
.Pan,
.Rdm,
.Vh,
.AggressiveFma,
.FpArmv8,
.Lse,
.Crc,
.Lor,
.UsePostraScheduler,
.ArithBccFusion,
.PredictableSelectExpensive,
}),
FeatureInfo(@This()).createWithSubfeatures(.Thunderxt81, "thunderxt81", "Cavium ThunderX processors", "thunderxt81", &[_]@This() {
.Perfmon,
.FpArmv8,
.Crc,
.UsePostraScheduler,
.PredictableSelectExpensive,
}),
FeatureInfo(@This()).createWithSubfeatures(.Thunderxt83, "thunderxt83", "Cavium ThunderX processors", "thunderxt83", &[_]@This() {
.Perfmon,
.FpArmv8,
.Crc,
.UsePostraScheduler,
.PredictableSelectExpensive,
}),
FeatureInfo(@This()).createWithSubfeatures(.Thunderxt88, "thunderxt88", "Cavium ThunderX processors", "thunderxt88", &[_]@This() {
.Perfmon,
.FpArmv8,
.Crc,
.UsePostraScheduler,
.PredictableSelectExpensive,
}),
};
};
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