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https://github.com/ziglang/zig.git
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452 lines
10 KiB
Zig
452 lines
10 KiB
Zig
const feature = @import("std").target.feature;
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const CpuInfo = @import("std").target.cpu.CpuInfo;
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pub const PowerPcCpu = enum {
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440,
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450,
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601,
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602,
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603,
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E603,
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Ev603,
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604,
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E604,
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620,
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7400,
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7450,
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750,
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970,
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A2,
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A2q,
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E500,
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E500mc,
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E5500,
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G3,
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G4,
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G4+,
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G5,
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Generic,
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Ppc,
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Ppc32,
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Ppc64,
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Ppc64le,
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Pwr3,
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Pwr4,
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Pwr5,
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Pwr5x,
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Pwr6,
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Pwr6x,
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Pwr7,
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Pwr8,
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Pwr9,
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pub fn getInfo(self: @This()) CpuInfo {
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return cpu_infos[@enumToInt(self)];
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}
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pub const FeatureType = feature.PowerPcFeature;
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const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
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CpuInfo(@This()).create(.440, "440", &[_]FeatureType {
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.Icbt,
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.Booke,
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.HardFloat,
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.Fres,
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.Frsqrte,
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.Isel,
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.Msync,
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},
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CpuInfo(@This()).create(.450, "450", &[_]FeatureType {
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.Icbt,
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.Booke,
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.HardFloat,
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.Fres,
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.Frsqrte,
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.Isel,
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.Msync,
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},
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CpuInfo(@This()).create(.601, "601", &[_]FeatureType {
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.HardFloat,
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.Fpu,
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},
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CpuInfo(@This()).create(.602, "602", &[_]FeatureType {
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.HardFloat,
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.Fpu,
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},
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CpuInfo(@This()).create(.603, "603", &[_]FeatureType {
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.HardFloat,
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.Fres,
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.Frsqrte,
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},
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CpuInfo(@This()).create(.E603, "603e", &[_]FeatureType {
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.HardFloat,
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.Fres,
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.Frsqrte,
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},
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CpuInfo(@This()).create(.Ev603, "603ev", &[_]FeatureType {
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.HardFloat,
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.Fres,
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.Frsqrte,
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},
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CpuInfo(@This()).create(.604, "604", &[_]FeatureType {
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.HardFloat,
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.Fres,
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.Frsqrte,
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},
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CpuInfo(@This()).create(.E604, "604e", &[_]FeatureType {
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.HardFloat,
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.Fres,
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.Frsqrte,
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},
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CpuInfo(@This()).create(.620, "620", &[_]FeatureType {
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.HardFloat,
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.Fres,
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.Frsqrte,
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},
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CpuInfo(@This()).create(.7400, "7400", &[_]FeatureType {
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.HardFloat,
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.Altivec,
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.Fres,
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.Frsqrte,
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},
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CpuInfo(@This()).create(.7450, "7450", &[_]FeatureType {
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.HardFloat,
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.Altivec,
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.Fres,
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.Frsqrte,
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},
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CpuInfo(@This()).create(.750, "750", &[_]FeatureType {
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.HardFloat,
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.Fres,
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.Frsqrte,
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},
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CpuInfo(@This()).create(.970, "970", &[_]FeatureType {
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.Bit64,
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.HardFloat,
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.Altivec,
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.Fres,
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.Frsqrte,
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.Fsqrt,
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.Mfocrf,
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.Stfiwx,
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},
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CpuInfo(@This()).create(.A2, "a2", &[_]FeatureType {
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.Bit64,
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.Icbt,
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.Booke,
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.Cmpb,
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.HardFloat,
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.Fcpsgn,
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.Fpcvt,
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.Fprnd,
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.Fre,
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.Fres,
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.Frsqrte,
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.Frsqrtes,
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.Fsqrt,
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.Isel,
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.Ldbrx,
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.Lfiwax,
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.Mfocrf,
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.Recipprec,
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.Stfiwx,
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.SlowPopcntd,
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},
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CpuInfo(@This()).create(.A2q, "a2q", &[_]FeatureType {
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.Bit64,
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.Icbt,
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.Booke,
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.Cmpb,
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.HardFloat,
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.Fcpsgn,
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.Fpcvt,
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.Fprnd,
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.Fre,
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.Fres,
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.Frsqrte,
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.Frsqrtes,
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.Fsqrt,
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.Isel,
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.Ldbrx,
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.Lfiwax,
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.Mfocrf,
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.Qpx,
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.Recipprec,
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.Stfiwx,
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.SlowPopcntd,
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},
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CpuInfo(@This()).create(.E500, "e500", &[_]FeatureType {
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.Icbt,
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.Booke,
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.Isel,
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},
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CpuInfo(@This()).create(.E500mc, "e500mc", &[_]FeatureType {
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.Icbt,
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.Booke,
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.Isel,
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.HardFloat,
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.Stfiwx,
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},
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CpuInfo(@This()).create(.E5500, "e5500", &[_]FeatureType {
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.Bit64,
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.Icbt,
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.Booke,
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.Isel,
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.Mfocrf,
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.HardFloat,
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.Stfiwx,
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},
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CpuInfo(@This()).create(.G3, "g3", &[_]FeatureType {
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.HardFloat,
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.Fres,
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.Frsqrte,
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},
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CpuInfo(@This()).create(.G4, "g4", &[_]FeatureType {
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.HardFloat,
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.Altivec,
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.Fres,
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.Frsqrte,
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},
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CpuInfo(@This()).create(.G4+, "g4+", &[_]FeatureType {
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.HardFloat,
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.Altivec,
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.Fres,
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.Frsqrte,
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},
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CpuInfo(@This()).create(.G5, "g5", &[_]FeatureType {
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.Bit64,
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.HardFloat,
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.Altivec,
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.Fres,
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.Frsqrte,
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.Fsqrt,
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.Mfocrf,
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.Stfiwx,
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},
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CpuInfo(@This()).create(.Generic, "generic", &[_]FeatureType {
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.HardFloat,
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},
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CpuInfo(@This()).create(.Ppc, "ppc", &[_]FeatureType {
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.HardFloat,
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},
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CpuInfo(@This()).create(.Ppc32, "ppc32", &[_]FeatureType {
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.HardFloat,
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},
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CpuInfo(@This()).create(.Ppc64, "ppc64", &[_]FeatureType {
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.Bit64,
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.HardFloat,
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.Altivec,
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.Fres,
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.Frsqrte,
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.Fsqrt,
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.Mfocrf,
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.Stfiwx,
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},
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CpuInfo(@This()).create(.Ppc64le, "ppc64le", &[_]FeatureType {
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.Bit64,
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.HardFloat,
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.Altivec,
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.Bpermd,
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.Cmpb,
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.DirectMove,
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.Extdiv,
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.Fcpsgn,
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.Fpcvt,
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.Fprnd,
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.Fre,
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.Fres,
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.Frsqrte,
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.Frsqrtes,
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.Fsqrt,
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.Htm,
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.Icbt,
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.Isel,
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.Ldbrx,
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.Lfiwax,
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.Mfocrf,
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.Power8Altivec,
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.Crypto,
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.Power8Vector,
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.Popcntd,
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.PartwordAtomics,
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.Recipprec,
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.Stfiwx,
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.TwoConstNr,
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.Vsx,
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},
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CpuInfo(@This()).create(.Pwr3, "pwr3", &[_]FeatureType {
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.Bit64,
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.HardFloat,
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.Altivec,
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.Fres,
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.Frsqrte,
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.Mfocrf,
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.Stfiwx,
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},
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CpuInfo(@This()).create(.Pwr4, "pwr4", &[_]FeatureType {
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.Bit64,
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.HardFloat,
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.Altivec,
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.Fres,
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.Frsqrte,
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.Fsqrt,
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.Mfocrf,
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.Stfiwx,
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},
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CpuInfo(@This()).create(.Pwr5, "pwr5", &[_]FeatureType {
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.Bit64,
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.HardFloat,
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.Altivec,
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.Fre,
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.Fres,
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.Frsqrte,
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.Frsqrtes,
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.Fsqrt,
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.Mfocrf,
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.Stfiwx,
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},
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CpuInfo(@This()).create(.Pwr5x, "pwr5x", &[_]FeatureType {
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.Bit64,
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.HardFloat,
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.Altivec,
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.Fprnd,
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.Fre,
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.Fres,
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.Frsqrte,
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.Frsqrtes,
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.Fsqrt,
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.Mfocrf,
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.Stfiwx,
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},
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CpuInfo(@This()).create(.Pwr6, "pwr6", &[_]FeatureType {
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.Bit64,
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.HardFloat,
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.Altivec,
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.Cmpb,
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.Fcpsgn,
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.Fprnd,
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.Fre,
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.Fres,
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.Frsqrte,
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.Frsqrtes,
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.Fsqrt,
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.Lfiwax,
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.Mfocrf,
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.Recipprec,
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.Stfiwx,
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},
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CpuInfo(@This()).create(.Pwr6x, "pwr6x", &[_]FeatureType {
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.Bit64,
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.HardFloat,
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.Altivec,
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.Cmpb,
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.Fcpsgn,
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.Fprnd,
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.Fre,
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.Fres,
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.Frsqrte,
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.Frsqrtes,
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.Fsqrt,
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.Lfiwax,
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.Mfocrf,
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.Recipprec,
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.Stfiwx,
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},
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CpuInfo(@This()).create(.Pwr7, "pwr7", &[_]FeatureType {
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.Bit64,
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.HardFloat,
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.Altivec,
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.Bpermd,
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.Cmpb,
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.Extdiv,
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.Fcpsgn,
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.Fpcvt,
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.Fprnd,
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.Fre,
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.Fres,
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.Frsqrte,
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.Frsqrtes,
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.Fsqrt,
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.Isel,
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.Ldbrx,
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.Lfiwax,
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.Mfocrf,
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.Popcntd,
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.Recipprec,
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.Stfiwx,
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.TwoConstNr,
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.Vsx,
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},
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CpuInfo(@This()).create(.Pwr8, "pwr8", &[_]FeatureType {
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.Bit64,
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.HardFloat,
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.Altivec,
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.Bpermd,
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.Cmpb,
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.DirectMove,
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.Extdiv,
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.Fcpsgn,
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.Fpcvt,
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.Fprnd,
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.Fre,
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.Fres,
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.Frsqrte,
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.Frsqrtes,
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.Fsqrt,
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.Htm,
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.Icbt,
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.Isel,
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.Ldbrx,
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.Lfiwax,
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.Mfocrf,
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.Power8Altivec,
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.Crypto,
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.Power8Vector,
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.Popcntd,
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.PartwordAtomics,
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.Recipprec,
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.Stfiwx,
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.TwoConstNr,
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.Vsx,
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},
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CpuInfo(@This()).create(.Pwr9, "pwr9", &[_]FeatureType {
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.Bit64,
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.HardFloat,
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.Altivec,
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.Bpermd,
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.Cmpb,
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.DirectMove,
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.Extdiv,
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.Fcpsgn,
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.Fpcvt,
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.Fprnd,
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.Fre,
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.Fres,
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.Frsqrte,
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.Frsqrtes,
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.Fsqrt,
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.Htm,
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.Icbt,
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.IsaV30Instructions,
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.Isel,
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.Ldbrx,
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.Lfiwax,
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.Mfocrf,
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.Power8Altivec,
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.Crypto,
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.Power8Vector,
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.Power9Altivec,
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.Power9Vector,
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.Popcntd,
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.PpcPostraSched,
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.PpcPreraSched,
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.PartwordAtomics,
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.Recipprec,
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.Stfiwx,
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.TwoConstNr,
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.Vsx,
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.VectorsUseTwoUnits,
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},
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};
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};
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