mirror of
https://github.com/ziglang/zig.git
synced 2026-01-15 20:05:16 +00:00
d55d98919d
Notable changes: `_i386`, `_i486`, and `_i686` are renamed to `i386`, `i486`, and `i686` respectively. `std.zig.fmtId` is enhanced to support formatting `i386` as `@"i386"`. Some CPU features which are actually CPU models have been properly flattened, such as `apple_a12`, `apple_a13`, `apple_a7`, `cortex_a78c`, `exynos_m4`, `neoverse_e1`, `neoverse_n1`, `neoverse_n2`, `neoverse_v1`. Some CPU features have been added and some have been removed, following LLVM's lead. CSky CPU features support is added.
563 lines
20 KiB
Zig
563 lines
20 KiB
Zig
const std = @import("std");
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const Target = std.Target;
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const CrossTarget = std.zig.CrossTarget;
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const XCR0_XMM = 0x02;
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const XCR0_YMM = 0x04;
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const XCR0_MASKREG = 0x20;
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const XCR0_ZMM0_15 = 0x40;
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const XCR0_ZMM16_31 = 0x80;
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fn setFeature(cpu: *Target.Cpu, feature: Target.x86.Feature, enabled: bool) void {
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const idx = @as(Target.Cpu.Feature.Set.Index, @enumToInt(feature));
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if (enabled) cpu.features.addFeature(idx) else cpu.features.removeFeature(idx);
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}
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inline fn bit(input: u32, offset: u5) bool {
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return (input >> offset) & 1 != 0;
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}
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inline fn hasMask(input: u32, mask: u32) bool {
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return (input & mask) == mask;
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}
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pub fn detectNativeCpuAndFeatures(arch: Target.Cpu.Arch, os: Target.Os, cross_target: CrossTarget) Target.Cpu {
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_ = cross_target;
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var cpu = Target.Cpu{
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.arch = arch,
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.model = Target.Cpu.Model.generic(arch),
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.features = Target.Cpu.Feature.Set.empty,
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};
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// First we detect features, to use as hints when detecting CPU Model.
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detectNativeFeatures(&cpu, os.tag);
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var leaf = cpuid(0, 0);
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const max_leaf = leaf.eax;
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const vendor = leaf.ebx;
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if (max_leaf > 0) {
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leaf = cpuid(0x1, 0);
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const brand_id = leaf.ebx & 0xff;
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// Detect model and family
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var family = (leaf.eax >> 8) & 0xf;
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var model = (leaf.eax >> 4) & 0xf;
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if (family == 6 or family == 0xf) {
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if (family == 0xf) {
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family += (leaf.eax >> 20) & 0xff;
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}
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model += ((leaf.eax >> 16) & 0xf) << 4;
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}
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// Now we detect the model.
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switch (vendor) {
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0x756e6547 => {
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detectIntelProcessor(&cpu, family, model, brand_id);
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},
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0x68747541 => {
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detectAMDProcessor(&cpu, family, model);
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},
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else => {},
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}
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}
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// Add the CPU model's feature set into the working set, but then
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// override with actual detected features again.
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cpu.features.addFeatureSet(cpu.model.features);
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detectNativeFeatures(&cpu, os.tag);
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cpu.features.populateDependencies(cpu.arch.allFeaturesList());
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return cpu;
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}
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fn detectIntelProcessor(cpu: *Target.Cpu, family: u32, model: u32, brand_id: u32) void {
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if (brand_id != 0) {
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return;
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}
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switch (family) {
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3 => {
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cpu.model = &Target.x86.cpu.i386;
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return;
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},
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4 => {
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cpu.model = &Target.x86.cpu.i486;
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return;
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},
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5 => {
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if (Target.x86.featureSetHas(cpu.features, .mmx)) {
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cpu.model = &Target.x86.cpu.pentium_mmx;
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return;
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}
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cpu.model = &Target.x86.cpu.pentium;
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return;
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},
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6 => {
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switch (model) {
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0x01 => {
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cpu.model = &Target.x86.cpu.pentiumpro;
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return;
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},
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0x03, 0x05, 0x06 => {
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cpu.model = &Target.x86.cpu.pentium2;
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return;
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},
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0x07, 0x08, 0x0a, 0x0b => {
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cpu.model = &Target.x86.cpu.pentium3;
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return;
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},
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0x09, 0x0d, 0x15 => {
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cpu.model = &Target.x86.cpu.pentium_m;
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return;
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},
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0x0e => {
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cpu.model = &Target.x86.cpu.yonah;
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return;
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},
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0x0f, 0x16 => {
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cpu.model = &Target.x86.cpu.core2;
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return;
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},
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0x17, 0x1d => {
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cpu.model = &Target.x86.cpu.penryn;
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return;
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},
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0x1a, 0x1e, 0x1f, 0x2e => {
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cpu.model = &Target.x86.cpu.nehalem;
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return;
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},
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0x25, 0x2c, 0x2f => {
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cpu.model = &Target.x86.cpu.westmere;
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return;
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},
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0x2a, 0x2d => {
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cpu.model = &Target.x86.cpu.sandybridge;
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return;
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},
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0x3a, 0x3e => {
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cpu.model = &Target.x86.cpu.ivybridge;
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return;
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},
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0x3c, 0x3f, 0x45, 0x46 => {
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cpu.model = &Target.x86.cpu.haswell;
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return;
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},
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0x3d, 0x47, 0x4f, 0x56 => {
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cpu.model = &Target.x86.cpu.broadwell;
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return;
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},
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0x4e, 0x5e, 0x8e, 0x9e => {
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cpu.model = &Target.x86.cpu.skylake;
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return;
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},
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0x55 => {
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if (Target.x86.featureSetHas(cpu.features, .avx512bf16)) {
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cpu.model = &Target.x86.cpu.cooperlake;
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return;
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} else if (Target.x86.featureSetHas(cpu.features, .avx512vnni)) {
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cpu.model = &Target.x86.cpu.cascadelake;
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return;
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} else {
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cpu.model = &Target.x86.cpu.skylake_avx512;
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return;
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}
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},
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0x66 => {
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cpu.model = &Target.x86.cpu.cannonlake;
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return;
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},
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0x7d, 0x7e => {
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cpu.model = &Target.x86.cpu.icelake_client;
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return;
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},
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0x6a, 0x6c => {
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cpu.model = &Target.x86.cpu.icelake_server;
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return;
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},
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0x1c, 0x26, 0x27, 0x35, 0x36 => {
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cpu.model = &Target.x86.cpu.bonnell;
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return;
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},
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0x37, 0x4a, 0x4d, 0x5a, 0x5d, 0x4c => {
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cpu.model = &Target.x86.cpu.silvermont;
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return;
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},
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0x5c, 0x5f => {
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cpu.model = &Target.x86.cpu.goldmont;
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return;
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},
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0x7a => {
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cpu.model = &Target.x86.cpu.goldmont_plus;
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return;
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},
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0x86 => {
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cpu.model = &Target.x86.cpu.tremont;
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return;
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},
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0x57 => {
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cpu.model = &Target.x86.cpu.knl;
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return;
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},
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0x85 => {
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cpu.model = &Target.x86.cpu.knm;
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return;
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},
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else => return, // Unknown CPU Model
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}
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},
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15 => {
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if (Target.x86.featureSetHas(cpu.features, .@"64bit")) {
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cpu.model = &Target.x86.cpu.nocona;
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return;
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}
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if (Target.x86.featureSetHas(cpu.features, .sse3)) {
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cpu.model = &Target.x86.cpu.prescott;
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return;
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}
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cpu.model = &Target.x86.cpu.pentium4;
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return;
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},
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else => return, // Unknown CPU Model
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}
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}
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fn detectAMDProcessor(cpu: *Target.Cpu, family: u32, model: u32) void {
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// AMD's cpuid information is less than optimal for determining a CPU model.
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// This is very unscientific, and not necessarily correct.
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switch (family) {
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4 => {
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cpu.model = &Target.x86.cpu.i486;
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return;
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},
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5 => {
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cpu.model = &Target.x86.cpu.pentium;
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switch (model) {
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6, 7 => {
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cpu.model = &Target.x86.cpu.k6;
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return;
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},
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8 => {
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cpu.model = &Target.x86.cpu.k6_2;
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return;
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},
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9, 13 => {
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cpu.model = &Target.x86.cpu.k6_3;
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return;
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},
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10 => {
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cpu.model = &Target.x86.cpu.geode;
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return;
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},
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else => {},
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}
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return;
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},
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6 => {
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if (Target.x86.featureSetHas(cpu.features, .sse)) {
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cpu.model = &Target.x86.cpu.athlon_xp;
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return;
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}
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cpu.model = &Target.x86.cpu.athlon;
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return;
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},
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15 => {
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if (Target.x86.featureSetHas(cpu.features, .sse3)) {
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cpu.model = &Target.x86.cpu.k8_sse3;
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return;
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}
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cpu.model = &Target.x86.cpu.k8;
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return;
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},
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16 => {
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cpu.model = &Target.x86.cpu.amdfam10;
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return;
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},
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20 => {
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cpu.model = &Target.x86.cpu.btver1;
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return;
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},
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21 => {
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cpu.model = &Target.x86.cpu.bdver1;
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if (model >= 0x60 and model <= 0x7f) {
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cpu.model = &Target.x86.cpu.bdver4;
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return;
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}
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if (model >= 0x30 and model <= 0x3f) {
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cpu.model = &Target.x86.cpu.bdver3;
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return;
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}
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if ((model >= 0x10 and model <= 0x1f) or model == 0x02) {
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cpu.model = &Target.x86.cpu.bdver2;
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return;
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}
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return;
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},
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22 => {
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cpu.model = &Target.x86.cpu.btver2;
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return;
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},
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23 => {
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cpu.model = &Target.x86.cpu.znver1;
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if ((model >= 0x30 and model <= 0x3f) or model == 0x71) {
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cpu.model = &Target.x86.cpu.znver2;
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return;
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}
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return;
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},
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25 => {
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cpu.model = &Target.x86.cpu.znver3;
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return;
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},
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else => {
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return;
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},
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}
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}
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fn detectNativeFeatures(cpu: *Target.Cpu, os_tag: Target.Os.Tag) void {
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var leaf = cpuid(0, 0);
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const max_level = leaf.eax;
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leaf = cpuid(1, 0);
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setFeature(cpu, .cx8, bit(leaf.edx, 8));
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setFeature(cpu, .cmov, bit(leaf.edx, 15));
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setFeature(cpu, .mmx, bit(leaf.edx, 23));
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setFeature(cpu, .fxsr, bit(leaf.edx, 24));
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setFeature(cpu, .sse, bit(leaf.edx, 25));
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setFeature(cpu, .sse2, bit(leaf.edx, 26));
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setFeature(cpu, .sse3, bit(leaf.ecx, 0));
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setFeature(cpu, .pclmul, bit(leaf.ecx, 1));
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setFeature(cpu, .ssse3, bit(leaf.ecx, 9));
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setFeature(cpu, .cx16, bit(leaf.ecx, 13));
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setFeature(cpu, .sse4_1, bit(leaf.ecx, 19));
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setFeature(cpu, .sse4_2, bit(leaf.ecx, 20));
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setFeature(cpu, .movbe, bit(leaf.ecx, 22));
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setFeature(cpu, .popcnt, bit(leaf.ecx, 23));
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setFeature(cpu, .aes, bit(leaf.ecx, 25));
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setFeature(cpu, .rdrnd, bit(leaf.ecx, 30));
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const has_xsave = bit(leaf.ecx, 27);
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const has_avx = bit(leaf.ecx, 28);
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// Make sure not to call xgetbv if xsave is not supported
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const xcr0_eax = if (has_xsave and has_avx) getXCR0() else 0;
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const has_avx_save = hasMask(xcr0_eax, XCR0_XMM | XCR0_YMM);
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// LLVM approaches avx512_save by hardcoding it to true on Darwin,
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// because the kernel saves the context even if the bit is not set.
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// https://github.com/llvm/llvm-project/blob/bca373f73fc82728a8335e7d6cd164e8747139ec/llvm/lib/Support/Host.cpp#L1378
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//
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// Google approaches this by using a different series of checks and flags,
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// and this may report the feature more accurately on a technically correct
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// but ultimately less useful level.
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// https://github.com/google/cpu_features/blob/b5c271c53759b2b15ff91df19bd0b32f2966e275/src/cpuinfo_x86.c#L113
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// (called from https://github.com/google/cpu_features/blob/b5c271c53759b2b15ff91df19bd0b32f2966e275/src/cpuinfo_x86.c#L1052)
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//
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// Right now, we use LLVM's approach, because even if the target doesn't support
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// the feature, the kernel should provide the same functionality transparently,
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// so the implementation details don't make a difference.
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// That said, this flag impacts other CPU features' availability,
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// so until we can verify that this doesn't come with side affects,
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// we'll say TODO verify this.
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// Darwin lazily saves the AVX512 context on first use: trust that the OS will
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// save the AVX512 context if we use AVX512 instructions, even if the bit is not
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// set right now.
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const has_avx512_save = switch (os_tag.isDarwin()) {
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true => true,
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false => hasMask(xcr0_eax, XCR0_MASKREG | XCR0_ZMM0_15 | XCR0_ZMM16_31),
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};
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setFeature(cpu, .avx, has_avx_save);
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setFeature(cpu, .fma, has_avx_save and bit(leaf.ecx, 12));
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// Only enable XSAVE if OS has enabled support for saving YMM state.
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setFeature(cpu, .xsave, has_avx_save and bit(leaf.ecx, 26));
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setFeature(cpu, .f16c, has_avx_save and bit(leaf.ecx, 29));
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leaf = cpuid(0x80000000, 0);
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const max_ext_level = leaf.eax;
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if (max_ext_level >= 0x80000001) {
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leaf = cpuid(0x80000001, 0);
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setFeature(cpu, .sahf, bit(leaf.ecx, 0));
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setFeature(cpu, .lzcnt, bit(leaf.ecx, 5));
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setFeature(cpu, .sse4a, bit(leaf.ecx, 6));
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setFeature(cpu, .prfchw, bit(leaf.ecx, 8));
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setFeature(cpu, .xop, bit(leaf.ecx, 11) and has_avx_save);
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setFeature(cpu, .lwp, bit(leaf.ecx, 15));
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setFeature(cpu, .fma4, bit(leaf.ecx, 16) and has_avx_save);
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setFeature(cpu, .tbm, bit(leaf.ecx, 21));
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setFeature(cpu, .mwaitx, bit(leaf.ecx, 29));
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setFeature(cpu, .@"64bit", bit(leaf.edx, 29));
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} else {
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for ([_]Target.x86.Feature{
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.sahf, .lzcnt, .sse4a, .prfchw, .xop,
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.lwp, .fma4, .tbm, .mwaitx, .@"64bit",
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}) |feat| {
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setFeature(cpu, feat, false);
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}
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}
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// Misc. memory-related features.
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if (max_ext_level >= 0x80000008) {
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leaf = cpuid(0x80000008, 0);
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setFeature(cpu, .clzero, bit(leaf.ebx, 0));
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setFeature(cpu, .wbnoinvd, bit(leaf.ebx, 9));
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} else {
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for ([_]Target.x86.Feature{ .clzero, .wbnoinvd }) |feat| {
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setFeature(cpu, feat, false);
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}
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}
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if (max_level >= 0x7) {
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leaf = cpuid(0x7, 0);
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setFeature(cpu, .fsgsbase, bit(leaf.ebx, 0));
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setFeature(cpu, .sgx, bit(leaf.ebx, 2));
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setFeature(cpu, .bmi, bit(leaf.ebx, 3));
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// AVX2 is only supported if we have the OS save support from AVX.
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setFeature(cpu, .avx2, bit(leaf.ebx, 5) and has_avx_save);
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setFeature(cpu, .bmi2, bit(leaf.ebx, 8));
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setFeature(cpu, .invpcid, bit(leaf.ebx, 10));
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setFeature(cpu, .rtm, bit(leaf.ebx, 11));
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// AVX512 is only supported if the OS supports the context save for it.
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setFeature(cpu, .avx512f, bit(leaf.ebx, 16) and has_avx512_save);
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setFeature(cpu, .avx512dq, bit(leaf.ebx, 17) and has_avx512_save);
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setFeature(cpu, .rdseed, bit(leaf.ebx, 18));
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setFeature(cpu, .adx, bit(leaf.ebx, 19));
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setFeature(cpu, .avx512ifma, bit(leaf.ebx, 21) and has_avx512_save);
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setFeature(cpu, .clflushopt, bit(leaf.ebx, 23));
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setFeature(cpu, .clwb, bit(leaf.ebx, 24));
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setFeature(cpu, .avx512pf, bit(leaf.ebx, 26) and has_avx512_save);
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setFeature(cpu, .avx512er, bit(leaf.ebx, 27) and has_avx512_save);
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setFeature(cpu, .avx512cd, bit(leaf.ebx, 28) and has_avx512_save);
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setFeature(cpu, .sha, bit(leaf.ebx, 29));
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setFeature(cpu, .avx512bw, bit(leaf.ebx, 30) and has_avx512_save);
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setFeature(cpu, .avx512vl, bit(leaf.ebx, 31) and has_avx512_save);
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setFeature(cpu, .prefetchwt1, bit(leaf.ecx, 0));
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setFeature(cpu, .avx512vbmi, bit(leaf.ecx, 1) and has_avx512_save);
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setFeature(cpu, .pku, bit(leaf.ecx, 4));
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setFeature(cpu, .waitpkg, bit(leaf.ecx, 5));
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setFeature(cpu, .avx512vbmi2, bit(leaf.ecx, 6) and has_avx512_save);
|
|
setFeature(cpu, .shstk, bit(leaf.ecx, 7));
|
|
setFeature(cpu, .gfni, bit(leaf.ecx, 8));
|
|
setFeature(cpu, .vaes, bit(leaf.ecx, 9) and has_avx_save);
|
|
setFeature(cpu, .vpclmulqdq, bit(leaf.ecx, 10) and has_avx_save);
|
|
setFeature(cpu, .avx512vnni, bit(leaf.ecx, 11) and has_avx512_save);
|
|
setFeature(cpu, .avx512bitalg, bit(leaf.ecx, 12) and has_avx512_save);
|
|
setFeature(cpu, .avx512vpopcntdq, bit(leaf.ecx, 14) and has_avx512_save);
|
|
setFeature(cpu, .avx512vp2intersect, bit(leaf.edx, 8) and has_avx512_save);
|
|
setFeature(cpu, .rdpid, bit(leaf.ecx, 22));
|
|
setFeature(cpu, .cldemote, bit(leaf.ecx, 25));
|
|
setFeature(cpu, .movdiri, bit(leaf.ecx, 27));
|
|
setFeature(cpu, .movdir64b, bit(leaf.ecx, 28));
|
|
setFeature(cpu, .enqcmd, bit(leaf.ecx, 29));
|
|
|
|
// There are two CPUID leafs which information associated with the pconfig
|
|
// instruction:
|
|
// EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th
|
|
// bit of EDX), while the EAX=0x1b leaf returns information on the
|
|
// availability of specific pconfig leafs.
|
|
// The target feature here only refers to the the first of these two.
|
|
// Users might need to check for the availability of specific pconfig
|
|
// leaves using cpuid, since that information is ignored while
|
|
// detecting features using the "-march=native" flag.
|
|
// For more info, see X86 ISA docs.
|
|
setFeature(cpu, .pconfig, bit(leaf.edx, 18));
|
|
|
|
// TODO I feel unsure about this check.
|
|
// It doesn't really seem to check for 7.1, just for 7.
|
|
// Is this a sound assumption to make?
|
|
// Note that this is what other implementations do, so I kind of trust it.
|
|
const has_leaf_7_1 = max_level >= 7;
|
|
if (has_leaf_7_1) {
|
|
leaf = cpuid(0x7, 0x1);
|
|
setFeature(cpu, .avx512bf16, bit(leaf.eax, 5) and has_avx512_save);
|
|
} else {
|
|
setFeature(cpu, .avx512bf16, false);
|
|
}
|
|
} else {
|
|
for ([_]Target.x86.Feature{
|
|
.fsgsbase, .sgx, .bmi, .avx2,
|
|
.bmi2, .invpcid, .rtm, .avx512f,
|
|
.avx512dq, .rdseed, .adx, .avx512ifma,
|
|
.clflushopt, .clwb, .avx512pf, .avx512er,
|
|
.avx512cd, .sha, .avx512bw, .avx512vl,
|
|
.prefetchwt1, .avx512vbmi, .pku, .waitpkg,
|
|
.avx512vbmi2, .shstk, .gfni, .vaes,
|
|
.vpclmulqdq, .avx512vnni, .avx512bitalg, .avx512vpopcntdq,
|
|
.avx512vp2intersect, .rdpid, .cldemote, .movdiri,
|
|
.movdir64b, .enqcmd, .pconfig, .avx512bf16,
|
|
}) |feat| {
|
|
setFeature(cpu, feat, false);
|
|
}
|
|
}
|
|
|
|
if (max_level >= 0xD and has_avx_save) {
|
|
leaf = cpuid(0xD, 0x1);
|
|
// Only enable XSAVE if OS has enabled support for saving YMM state.
|
|
setFeature(cpu, .xsaveopt, bit(leaf.eax, 0));
|
|
setFeature(cpu, .xsavec, bit(leaf.eax, 1));
|
|
setFeature(cpu, .xsaves, bit(leaf.eax, 3));
|
|
} else {
|
|
for ([_]Target.x86.Feature{ .xsaveopt, .xsavec, .xsaves }) |feat| {
|
|
setFeature(cpu, feat, false);
|
|
}
|
|
}
|
|
|
|
if (max_level >= 0x14) {
|
|
leaf = cpuid(0x14, 0);
|
|
setFeature(cpu, .ptwrite, bit(leaf.ebx, 4));
|
|
} else {
|
|
setFeature(cpu, .ptwrite, false);
|
|
}
|
|
}
|
|
|
|
const CpuidLeaf = packed struct {
|
|
eax: u32,
|
|
ebx: u32,
|
|
ecx: u32,
|
|
edx: u32,
|
|
};
|
|
|
|
fn cpuid(leaf_id: u32, subid: u32) CpuidLeaf {
|
|
// Workaround for https://github.com/ziglang/zig/issues/215
|
|
// Inline assembly in zig only supports one output,
|
|
// so we pass a pointer to the struct.
|
|
var cpuid_leaf: CpuidLeaf = undefined;
|
|
|
|
// valid for both x86 and x86_64
|
|
asm volatile (
|
|
\\ cpuid
|
|
\\ movl %%eax, 0(%[leaf_ptr])
|
|
\\ movl %%ebx, 4(%[leaf_ptr])
|
|
\\ movl %%ecx, 8(%[leaf_ptr])
|
|
\\ movl %%edx, 12(%[leaf_ptr])
|
|
:
|
|
: [leaf_id] "{eax}" (leaf_id),
|
|
[subid] "{ecx}" (subid),
|
|
[leaf_ptr] "r" (&cpuid_leaf),
|
|
: "eax", "ebx", "ecx", "edx"
|
|
);
|
|
|
|
return cpuid_leaf;
|
|
}
|
|
|
|
// Read control register 0 (XCR0). Used to detect features such as AVX.
|
|
fn getXCR0() u32 {
|
|
return asm volatile (
|
|
\\ xor %%ecx, %%ecx
|
|
\\ xgetbv
|
|
: [ret] "={eax}" (-> u32),
|
|
:
|
|
: "eax", "edx", "ecx"
|
|
);
|
|
}
|