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635a3d87de
This target triple was weird on multiple levels: * The `ilp32` ABI is the soft float ABI. This is not the main ABI we want to support on RISC-V; rather, we want `ilp32d`. * `gnuilp32` is a bespoke tag that was introduced in Zig. The rest of the world just uses `gnu` for RISC-V target triples. * `gnu_ilp32` is already the name of an ILP32 ABI used on AArch64. `gnuilp32` is too easy to confuse with this. * We don't use this convention for `riscv64-linux-gnu`. * Supporting all RISC-V ABIs with this convention will result in combinatorial explosion; see #20690.
74 lines
2.6 KiB
C
Vendored
74 lines
2.6 KiB
C
Vendored
/* FPU control word bits. RISC-V version.
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Copyright (C) 1996-2024 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library. If not, see
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<https://www.gnu.org/licenses/>. */
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#ifndef _FPU_CONTROL_H
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#define _FPU_CONTROL_H
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#include <features.h>
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#ifndef __riscv_flen
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# define _FPU_RESERVED 0xffffffff
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# define _FPU_DEFAULT 0x00000000
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typedef unsigned int fpu_control_t;
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# define _FPU_GETCW(cw) (cw) = 0
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# define _FPU_SETCW(cw) do { } while (0)
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extern fpu_control_t __fpu_control;
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#else /* __riscv_flen */
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# define _FPU_RESERVED 0
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# define _FPU_DEFAULT 0
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# define _FPU_IEEE _FPU_DEFAULT
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/* Type of the control word. */
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typedef unsigned int fpu_control_t __attribute__ ((__mode__ (__SI__)));
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/* Macros for accessing the hardware control word. */
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# define _FPU_GETCW(cw) __asm__ volatile ("frsr %0" : "=r" (cw))
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# define _FPU_SETCW(cw) __asm__ volatile ("fssr %z0" : : "rJ" (cw))
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/* Default control word set at startup. */
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extern fpu_control_t __fpu_control;
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# define _FCLASS(x) (__extension__ ({ int __res; \
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if (sizeof (x) * 8 > __riscv_flen) __builtin_trap (); \
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if (sizeof (x) == 4) asm ("fclass.s %0, %1" : "=r" (__res) : "f" (x)); \
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else if (sizeof (x) == 8) asm ("fclass.d %0, %1" : "=r" (__res) : "f" (x)); \
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else __builtin_trap (); \
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__res; }))
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# define _FCLASS_MINF (1 << 0)
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# define _FCLASS_MNORM (1 << 1)
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# define _FCLASS_MSUBNORM (1 << 2)
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# define _FCLASS_MZERO (1 << 3)
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# define _FCLASS_PZERO (1 << 4)
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# define _FCLASS_PSUBNORM (1 << 5)
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# define _FCLASS_PNORM (1 << 6)
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# define _FCLASS_PINF (1 << 7)
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# define _FCLASS_SNAN (1 << 8)
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# define _FCLASS_QNAN (1 << 9)
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# define _FCLASS_ZERO (_FCLASS_MZERO | _FCLASS_PZERO)
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# define _FCLASS_SUBNORM (_FCLASS_MSUBNORM | _FCLASS_PSUBNORM)
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# define _FCLASS_NORM (_FCLASS_MNORM | _FCLASS_PNORM)
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# define _FCLASS_INF (_FCLASS_MINF | _FCLASS_PINF)
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# define _FCLASS_NAN (_FCLASS_SNAN | _FCLASS_QNAN)
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#endif /* __riscv_flen */
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#endif /* fpu_control.h */ |