mirror of
https://github.com/ziglang/zig.git
synced 2025-12-27 08:33:15 +00:00
6146abee1e
Implements lowering for the add_with_overflow AIR instructions. Also implements a helper function, simpleStructType, to quickly generate a SPIR-V structure type without having to do the whole allocation dance.
1516 lines
65 KiB
Zig
1516 lines
65 KiB
Zig
const std = @import("std");
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const Allocator = std.mem.Allocator;
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const Target = std.Target;
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const log = std.log.scoped(.codegen);
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const assert = std.debug.assert;
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const Module = @import("../Module.zig");
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const Decl = Module.Decl;
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const Type = @import("../type.zig").Type;
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const Value = @import("../value.zig").Value;
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const LazySrcLoc = Module.LazySrcLoc;
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const Air = @import("../Air.zig");
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const Zir = @import("../Zir.zig");
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const Liveness = @import("../Liveness.zig");
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const spec = @import("spirv/spec.zig");
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const Opcode = spec.Opcode;
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const Word = spec.Word;
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const IdRef = spec.IdRef;
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const IdResult = spec.IdResult;
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const IdResultType = spec.IdResultType;
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const SpvModule = @import("spirv/Module.zig");
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const SpvSection = @import("spirv/Section.zig");
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const SpvType = @import("spirv/type.zig").Type;
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const SpvAssembler = @import("spirv/Assembler.zig");
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const InstMap = std.AutoHashMapUnmanaged(Air.Inst.Index, IdRef);
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const IncomingBlock = struct {
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src_label_id: IdRef,
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break_value_id: IdRef,
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};
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pub const BlockMap = std.AutoHashMapUnmanaged(Air.Inst.Index, struct {
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label_id: IdRef,
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incoming_blocks: *std.ArrayListUnmanaged(IncomingBlock),
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});
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/// This structure is used to compile a declaration, and contains all relevant meta-information to deal with that.
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pub const DeclGen = struct {
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/// A general-purpose allocator that can be used for any allocations for this DeclGen.
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gpa: Allocator,
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/// The Zig module that we are generating decls for.
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module: *Module,
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/// The SPIR-V module that instructions should be emitted into.
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spv: *SpvModule,
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/// The decl we are currently generating code for.
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decl_index: Decl.Index,
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/// The intermediate code of the declaration we are currently generating. Note: If
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/// the declaration is not a function, this value will be undefined!
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air: Air,
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/// The liveness analysis of the intermediate code for the declaration we are currently generating.
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/// Note: If the declaration is not a function, this value will be undefined!
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liveness: Liveness,
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ids: *const std.AutoHashMap(Decl.Index, IdResult),
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/// An array of function argument result-ids. Each index corresponds with the
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/// function argument of the same index.
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args: std.ArrayListUnmanaged(IdRef) = .{},
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/// A counter to keep track of how many `arg` instructions we've seen yet.
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next_arg_index: u32,
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/// A map keeping track of which instruction generated which result-id.
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inst_results: InstMap = .{},
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/// We need to keep track of result ids for block labels, as well as the 'incoming'
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/// blocks for a block.
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blocks: BlockMap = .{},
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/// The label of the SPIR-V block we are currently generating.
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current_block_label_id: IdRef,
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/// The code (prologue and body) for the function we are currently generating code for.
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func: SpvModule.Fn = .{},
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/// If `gen` returned `Error.CodegenFail`, this contains an explanatory message.
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/// Memory is owned by `module.gpa`.
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error_msg: ?*Module.ErrorMsg,
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/// Possible errors the `genDecl` function may return.
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const Error = error{ CodegenFail, OutOfMemory };
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/// This structure is used to return information about a type typically used for
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/// arithmetic operations. These types may either be integers, floats, or a vector
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/// of these. Most scalar operations also work on vectors, so we can easily represent
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/// those as arithmetic types. If the type is a scalar, 'inner type' refers to the
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/// scalar type. Otherwise, if its a vector, it refers to the vector's element type.
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const ArithmeticTypeInfo = struct {
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/// A classification of the inner type.
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const Class = enum {
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/// A boolean.
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bool,
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/// A regular, **native**, integer.
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/// This is only returned when the backend supports this int as a native type (when
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/// the relevant capability is enabled).
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integer,
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/// A regular float. These are all required to be natively supported. Floating points
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/// for which the relevant capability is not enabled are not emulated.
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float,
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/// An integer of a 'strange' size (which' bit size is not the same as its backing
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/// type. **Note**: this may **also** include power-of-2 integers for which the
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/// relevant capability is not enabled), but still within the limits of the largest
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/// natively supported integer type.
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strange_integer,
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/// An integer with more bits than the largest natively supported integer type.
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composite_integer,
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};
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/// The number of bits in the inner type.
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/// This is the actual number of bits of the type, not the size of the backing integer.
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bits: u16,
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/// Whether the type is a vector.
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is_vector: bool,
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/// Whether the inner type is signed. Only relevant for integers.
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signedness: std.builtin.Signedness,
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/// A classification of the inner type. These scenarios
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/// will all have to be handled slightly different.
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class: Class,
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};
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/// Initialize the common resources of a DeclGen. Some fields are left uninitialized,
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/// only set when `gen` is called.
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pub fn init(
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allocator: Allocator,
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module: *Module,
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spv: *SpvModule,
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ids: *const std.AutoHashMap(Decl.Index, IdResult),
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) DeclGen {
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return .{
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.gpa = allocator,
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.module = module,
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.spv = spv,
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.decl_index = undefined,
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.air = undefined,
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.liveness = undefined,
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.ids = ids,
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.next_arg_index = undefined,
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.current_block_label_id = undefined,
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.error_msg = undefined,
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};
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}
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/// Generate the code for `decl`. If a reportable error occurred during code generation,
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/// a message is returned by this function. Callee owns the memory. If this function
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/// returns such a reportable error, it is valid to be called again for a different decl.
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pub fn gen(self: *DeclGen, decl_index: Decl.Index, air: Air, liveness: Liveness) !?*Module.ErrorMsg {
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// Reset internal resources, we don't want to re-allocate these.
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self.decl_index = decl_index;
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self.air = air;
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self.liveness = liveness;
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self.args.items.len = 0;
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self.next_arg_index = 0;
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self.inst_results.clearRetainingCapacity();
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self.blocks.clearRetainingCapacity();
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self.current_block_label_id = undefined;
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self.func.reset();
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self.error_msg = null;
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self.genDecl() catch |err| switch (err) {
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error.CodegenFail => return self.error_msg,
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else => |others| {
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// There might be an error that happened *after* self.error_msg
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// was already allocated, so be sure to free it.
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if (self.error_msg) |error_msg| {
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error_msg.deinit(self.module.gpa);
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}
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return others;
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},
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};
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return null;
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}
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/// Free resources owned by the DeclGen.
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pub fn deinit(self: *DeclGen) void {
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self.args.deinit(self.gpa);
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self.inst_results.deinit(self.gpa);
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self.blocks.deinit(self.gpa);
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self.func.deinit(self.gpa);
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}
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/// Return the target which we are currently compiling for.
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pub fn getTarget(self: *DeclGen) std.Target {
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return self.module.getTarget();
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}
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pub fn fail(self: *DeclGen, comptime format: []const u8, args: anytype) Error {
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@setCold(true);
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const src = LazySrcLoc.nodeOffset(0);
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const src_loc = src.toSrcLoc(self.module.declPtr(self.decl_index));
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assert(self.error_msg == null);
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self.error_msg = try Module.ErrorMsg.create(self.module.gpa, src_loc, format, args);
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return error.CodegenFail;
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}
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pub fn todo(self: *DeclGen, comptime format: []const u8, args: anytype) Error {
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return self.fail("TODO (SPIR-V): " ++ format, args);
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}
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/// Fetch the result-id for a previously generated instruction or constant.
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fn resolve(self: *DeclGen, inst: Air.Inst.Ref) !IdRef {
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if (self.air.value(inst)) |val| {
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return self.genConstant(self.air.typeOf(inst), val);
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}
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const index = Air.refToIndex(inst).?;
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return self.inst_results.get(index).?; // Assertion means instruction does not dominate usage.
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}
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/// Start a new SPIR-V block, Emits the label of the new block, and stores which
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/// block we are currently generating.
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/// Note that there is no such thing as nested blocks like in ZIR or AIR, so we don't need to
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/// keep track of the previous block.
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fn beginSpvBlock(self: *DeclGen, label_id: IdResult) !void {
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try self.func.body.emit(self.spv.gpa, .OpLabel, .{ .id_result = label_id });
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self.current_block_label_id = label_id.toRef();
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}
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/// SPIR-V requires enabling specific integer sizes through capabilities, and so if they are not enabled, we need
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/// to emulate them in other instructions/types. This function returns, given an integer bit width (signed or unsigned, sign
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/// included), the width of the underlying type which represents it, given the enabled features for the current target.
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/// If the result is `null`, the largest type the target platform supports natively is not able to perform computations using
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/// that size. In this case, multiple elements of the largest type should be used.
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/// The backing type will be chosen as the smallest supported integer larger or equal to it in number of bits.
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/// The result is valid to be used with OpTypeInt.
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/// TODO: The extension SPV_INTEL_arbitrary_precision_integers allows any integer size (at least up to 32 bits).
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/// TODO: This probably needs an ABI-version as well (especially in combination with SPV_INTEL_arbitrary_precision_integers).
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/// TODO: Should the result of this function be cached?
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fn backingIntBits(self: *DeclGen, bits: u16) ?u16 {
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const target = self.getTarget();
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// The backend will never be asked to compiler a 0-bit integer, so we won't have to handle those in this function.
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assert(bits != 0);
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// 8, 16 and 64-bit integers require the Int8, Int16 and Inr64 capabilities respectively.
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// 32-bit integers are always supported (see spec, 2.16.1, Data rules).
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const ints = [_]struct { bits: u16, feature: ?Target.spirv.Feature }{
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.{ .bits = 8, .feature = .Int8 },
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.{ .bits = 16, .feature = .Int16 },
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.{ .bits = 32, .feature = null },
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.{ .bits = 64, .feature = .Int64 },
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};
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for (ints) |int| {
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const has_feature = if (int.feature) |feature|
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Target.spirv.featureSetHas(target.cpu.features, feature)
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else
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true;
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if (bits <= int.bits and has_feature) {
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return int.bits;
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}
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}
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return null;
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}
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/// Return the amount of bits in the largest supported integer type. This is either 32 (always supported), or 64 (if
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/// the Int64 capability is enabled).
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/// Note: The extension SPV_INTEL_arbitrary_precision_integers allows any integer size (at least up to 32 bits).
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/// In theory that could also be used, but since the spec says that it only guarantees support up to 32-bit ints there
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/// is no way of knowing whether those are actually supported.
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/// TODO: Maybe this should be cached?
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fn largestSupportedIntBits(self: *DeclGen) u16 {
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const target = self.getTarget();
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return if (Target.spirv.featureSetHas(target.cpu.features, .Int64))
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64
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else
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32;
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}
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/// Checks whether the type is "composite int", an integer consisting of multiple native integers. These are represented by
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/// arrays of largestSupportedIntBits().
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/// Asserts `ty` is an integer.
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fn isCompositeInt(self: *DeclGen, ty: Type) bool {
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return self.backingIntBits(ty) == null;
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}
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fn arithmeticTypeInfo(self: *DeclGen, ty: Type) !ArithmeticTypeInfo {
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const target = self.getTarget();
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return switch (ty.zigTypeTag()) {
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.Bool => ArithmeticTypeInfo{
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.bits = 1, // Doesn't matter for this class.
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.is_vector = false,
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.signedness = .unsigned, // Technically, but doesn't matter for this class.
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.class = .bool,
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},
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.Float => ArithmeticTypeInfo{
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.bits = ty.floatBits(target),
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.is_vector = false,
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.signedness = .signed, // Technically, but doesn't matter for this class.
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.class = .float,
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},
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.Int => blk: {
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const int_info = ty.intInfo(target);
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// TODO: Maybe it's useful to also return this value.
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const maybe_backing_bits = self.backingIntBits(int_info.bits);
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break :blk ArithmeticTypeInfo{
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.bits = int_info.bits,
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.is_vector = false,
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.signedness = int_info.signedness,
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.class = if (maybe_backing_bits) |backing_bits|
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if (backing_bits == int_info.bits)
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ArithmeticTypeInfo.Class.integer
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else
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ArithmeticTypeInfo.Class.strange_integer
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else
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.composite_integer,
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};
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},
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// As of yet, there is no vector support in the self-hosted compiler.
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.Vector => self.todo("implement arithmeticTypeInfo for Vector", .{}),
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// TODO: For which types is this the case?
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else => self.todo("implement arithmeticTypeInfo for {}", .{ty.fmtDebug()}),
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};
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}
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/// Generate a constant representing `val`.
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/// TODO: Deduplication?
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fn genConstant(self: *DeclGen, ty: Type, val: Value) Error!IdRef {
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if (ty.zigTypeTag() == .Fn) {
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const fn_decl_index = switch (val.tag()) {
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.extern_fn => val.castTag(.extern_fn).?.data.owner_decl,
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.function => val.castTag(.function).?.data.owner_decl,
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else => unreachable,
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};
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const decl = self.module.declPtr(fn_decl_index);
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self.module.markDeclAlive(decl);
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return self.ids.get(fn_decl_index).?.toRef();
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}
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const target = self.getTarget();
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const section = &self.spv.sections.types_globals_constants;
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const result_id = self.spv.allocId();
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const result_type_id = try self.resolveTypeId(ty);
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if (val.isUndef()) {
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try section.emit(self.spv.gpa, .OpUndef, .{ .id_result_type = result_type_id, .id_result = result_id });
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return result_id.toRef();
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}
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switch (ty.zigTypeTag()) {
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.Int => {
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const int_info = ty.intInfo(target);
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const backing_bits = self.backingIntBits(int_info.bits) orelse {
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// Integers too big for any native type are represented as "composite integers": An array of largestSupportedIntBits.
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return self.todo("implement composite int constants for {}", .{ty.fmtDebug()});
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};
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// We can just use toSignedInt/toUnsignedInt here as it returns u64 - a type large enough to hold any
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// SPIR-V native type (up to i/u64 with Int64). If SPIR-V ever supports native ints of a larger size, this
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// might need to be updated.
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assert(self.largestSupportedIntBits() <= @bitSizeOf(u64));
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// Note, value is required to be sign-extended, so we don't need to mask off the upper bits.
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// See https://www.khronos.org/registry/SPIR-V/specs/unified1/SPIRV.html#Literal
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var int_bits = if (ty.isSignedInt()) @bitCast(u64, val.toSignedInt(target)) else val.toUnsignedInt(target);
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const value: spec.LiteralContextDependentNumber = switch (backing_bits) {
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1...32 => .{ .uint32 = @truncate(u32, int_bits) },
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33...64 => .{ .uint64 = int_bits },
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else => unreachable,
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};
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try section.emit(self.spv.gpa, .OpConstant, .{
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.id_result_type = result_type_id,
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.id_result = result_id,
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.value = value,
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});
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},
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.Bool => {
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const operands = .{ .id_result_type = result_type_id, .id_result = result_id };
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if (val.toBool()) {
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try section.emit(self.spv.gpa, .OpConstantTrue, operands);
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} else {
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try section.emit(self.spv.gpa, .OpConstantFalse, operands);
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}
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},
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.Float => {
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// At this point we are guaranteed that the target floating point type is supported, otherwise the function
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// would have exited at resolveTypeId(ty).
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const value: spec.LiteralContextDependentNumber = switch (ty.floatBits(target)) {
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// Prevent upcasting to f32 by bitcasting and writing as a uint32.
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16 => .{ .uint32 = @bitCast(u16, val.toFloat(f16)) },
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32 => .{ .float32 = val.toFloat(f32) },
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64 => .{ .float64 = val.toFloat(f64) },
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128 => unreachable, // Filtered out in the call to resolveTypeId.
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// TODO: Insert case for long double when the layout for that is determined?
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else => unreachable,
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};
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try section.emit(self.spv.gpa, .OpConstant, .{
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.id_result_type = result_type_id,
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.id_result = result_id,
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.value = value,
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});
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},
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.Vector => switch (val.tag()) {
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.aggregate => {
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const elem_vals = val.castTag(.aggregate).?.data;
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const vector_len = @intCast(usize, ty.vectorLen());
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const elem_ty = ty.elemType();
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const elem_refs = try self.gpa.alloc(IdRef, vector_len);
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defer self.gpa.free(elem_refs);
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for (elem_refs, 0..) |*elem, i| {
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elem.* = try self.genConstant(elem_ty, elem_vals[i]);
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}
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try section.emit(self.spv.gpa, .OpConstantComposite, .{
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.id_result_type = result_type_id,
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.id_result = result_id,
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.constituents = elem_refs,
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});
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},
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else => unreachable, // TODO
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},
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.Void => unreachable,
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.Fn => unreachable,
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else => return self.todo("constant generation of type {}", .{ty.fmtDebug()}),
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}
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return result_id.toRef();
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}
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/// Turn a Zig type into a SPIR-V Type, and return its type result-id.
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fn resolveTypeId(self: *DeclGen, ty: Type) !IdResultType {
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const type_ref = try self.resolveType(ty);
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return self.spv.typeResultId(type_ref);
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}
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/// Create an integer type suitable for storing at least 'bits' bits.
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fn intType(self: *DeclGen, signedness: std.builtin.Signedness, bits: u16) !SpvType.Ref {
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const backing_bits = self.backingIntBits(bits) orelse {
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// TODO: Integers too big for any native type are represented as "composite integers":
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// An array of largestSupportedIntBits.
|
|
return self.todo("Implement {s} composite int type of {} bits", .{ @tagName(signedness), bits });
|
|
};
|
|
|
|
return try self.spv.resolveType(try SpvType.int(self.spv.arena, signedness, backing_bits));
|
|
}
|
|
|
|
/// Create an integer type that represents 'usize'.
|
|
fn sizeType(self: *DeclGen) !SpvType.Ref {
|
|
return try self.intType(.unsigned, self.getTarget().cpu.arch.ptrBitWidth());
|
|
}
|
|
|
|
/// Construct a simple struct type which consists of some members, and no decorations.
|
|
/// `members` lifetime only needs to last for this function as it is copied.
|
|
fn simpleStructType(self: *DeclGen, members: []const SpvType.Payload.Struct.Member) !SpvType.Ref {
|
|
const payload = try self.spv.arena.create(SpvType.Payload.Struct);
|
|
payload.* = .{
|
|
.members = try self.spv.arena.dupe(SpvType.Payload.Struct.Member, members),
|
|
.decorations = .{},
|
|
};
|
|
return try self.spv.resolveType(SpvType.initPayload(&payload.base));
|
|
}
|
|
|
|
fn simpleStructTypeId(self: *DeclGen, members: []const SpvType.Payload.Struct.Member) !IdResultType {
|
|
const type_ref = try self.simpleStructType(members);
|
|
return self.spv.typeResultId(type_ref);
|
|
}
|
|
|
|
/// Turn a Zig type into a SPIR-V Type, and return a reference to it.
|
|
fn resolveType(self: *DeclGen, ty: Type) Error!SpvType.Ref {
|
|
const target = self.getTarget();
|
|
switch (ty.zigTypeTag()) {
|
|
.Void, .NoReturn => return try self.spv.resolveType(SpvType.initTag(.void)),
|
|
.Bool => {
|
|
// TODO: SPIR-V booleans are opaque. For local variables this is fine, but for structs
|
|
// members we want to use integer types instead.
|
|
return try self.spv.resolveType(SpvType.initTag(.bool));
|
|
},
|
|
.Int => {
|
|
const int_info = ty.intInfo(target);
|
|
return try self.intType(int_info.signedness, int_info.bits);
|
|
},
|
|
.Enum => {
|
|
var buffer: Type.Payload.Bits = undefined;
|
|
const int_ty = ty.intTagType(&buffer);
|
|
const int_info = int_ty.intInfo(target);
|
|
return try self.intType(.unsigned, int_info.bits);
|
|
},
|
|
.Float => {
|
|
// We can (and want) not really emulate floating points with other floating point types like with the integer types,
|
|
// so if the float is not supported, just return an error.
|
|
const bits = ty.floatBits(target);
|
|
const supported = switch (bits) {
|
|
16 => Target.spirv.featureSetHas(target.cpu.features, .Float16),
|
|
// 32-bit floats are always supported (see spec, 2.16.1, Data rules).
|
|
32 => true,
|
|
64 => Target.spirv.featureSetHas(target.cpu.features, .Float64),
|
|
else => false,
|
|
};
|
|
|
|
if (!supported) {
|
|
return self.fail("Floating point width of {} bits is not supported for the current SPIR-V feature set", .{bits});
|
|
}
|
|
|
|
return try self.spv.resolveType(SpvType.float(bits));
|
|
},
|
|
.Array => {
|
|
const elem_ty = ty.childType();
|
|
const total_len_u64 = ty.arrayLen() + @boolToInt(ty.sentinel() != null);
|
|
const total_len = std.math.cast(u32, total_len_u64) orelse {
|
|
return self.fail("array type of {} elements is too large", .{total_len_u64});
|
|
};
|
|
|
|
const payload = try self.spv.arena.create(SpvType.Payload.Array);
|
|
payload.* = .{
|
|
.element_type = try self.resolveType(elem_ty),
|
|
.length = total_len,
|
|
.array_stride = @intCast(u32, ty.abiSize(target)),
|
|
};
|
|
return try self.spv.resolveType(SpvType.initPayload(&payload.base));
|
|
},
|
|
.Fn => {
|
|
// TODO: Put this somewhere in Sema.zig
|
|
if (ty.fnIsVarArgs())
|
|
return self.fail("VarArgs functions are unsupported for SPIR-V", .{});
|
|
|
|
const param_types = try self.spv.arena.alloc(SpvType.Ref, ty.fnParamLen());
|
|
for (param_types, 0..) |*param, i| {
|
|
param.* = try self.resolveType(ty.fnParamType(i));
|
|
}
|
|
|
|
const return_type = try self.resolveType(ty.fnReturnType());
|
|
|
|
const payload = try self.spv.arena.create(SpvType.Payload.Function);
|
|
payload.* = .{ .return_type = return_type, .parameters = param_types };
|
|
return try self.spv.resolveType(SpvType.initPayload(&payload.base));
|
|
},
|
|
.Pointer => {
|
|
const ptr_info = ty.ptrInfo().data;
|
|
|
|
const ptr_payload = try self.spv.arena.create(SpvType.Payload.Pointer);
|
|
ptr_payload.* = .{
|
|
.storage_class = spirvStorageClass(ptr_info.@"addrspace"),
|
|
.child_type = try self.resolveType(ptr_info.pointee_type),
|
|
// TODO: ???
|
|
.array_stride = 0,
|
|
// Note: only available in Kernels!
|
|
.alignment = ty.ptrAlignment(target) * 8,
|
|
.max_byte_offset = null,
|
|
};
|
|
const spv_ptr_ty = try self.spv.resolveType(SpvType.initPayload(&ptr_payload.base));
|
|
|
|
if (ptr_info.size != .Slice) {
|
|
return spv_ptr_ty;
|
|
}
|
|
|
|
var buf: Type.SlicePtrFieldTypeBuffer = undefined;
|
|
const ptr_ty = ty.slicePtrFieldType(&buf);
|
|
const len_ty = Type.usize;
|
|
|
|
const ptr_size = ptr_ty.abiSize(target);
|
|
const len_align = len_ty.abiAlignment(target);
|
|
const len_offset = std.mem.alignForwardGeneric(u64, ptr_size, len_align);
|
|
|
|
return try self.simpleStructType(&.{
|
|
.{ .ty = spv_ptr_ty, .offset = 0 },
|
|
.{ .ty = try self.sizeType(), .offset = @intCast(u32, len_offset) },
|
|
});
|
|
},
|
|
.Vector => {
|
|
// Although not 100% the same, Zig vectors map quite neatly to SPIR-V vectors (including many integer and float operations
|
|
// which work on them), so simply use those.
|
|
// Note: SPIR-V vectors only support bools, ints and floats, so pointer vectors need to be supported another way.
|
|
// "composite integers" (larger than the largest supported native type) can probably be represented by an array of vectors.
|
|
// TODO: The SPIR-V spec mentions that vector sizes may be quite restricted! look into which we can use, and whether OpTypeVector
|
|
// is adequate at all for this.
|
|
|
|
// TODO: Properly verify sizes and child type.
|
|
|
|
const payload = try self.spv.arena.create(SpvType.Payload.Vector);
|
|
payload.* = .{
|
|
.component_type = try self.resolveType(ty.elemType()),
|
|
.component_count = @intCast(u32, ty.vectorLen()),
|
|
};
|
|
return try self.spv.resolveType(SpvType.initPayload(&payload.base));
|
|
},
|
|
.Struct => {
|
|
if (ty.isSimpleTupleOrAnonStruct()) {
|
|
const tuple = ty.tupleFields();
|
|
const members = try self.spv.arena.alloc(SpvType.Payload.Struct.Member, tuple.types.len);
|
|
var member_index: usize = 0;
|
|
for (tuple.types) |field_ty, i| {
|
|
const field_val = tuple.values[i];
|
|
if (field_val.tag() != .unreachable_value or !field_ty.hasRuntimeBits()) continue;
|
|
|
|
members[member_index] = .{
|
|
.ty = try self.resolveType(field_ty),
|
|
.offset = 0,
|
|
};
|
|
}
|
|
|
|
const payload = try self.spv.arena.create(SpvType.Payload.Struct);
|
|
payload.* = .{
|
|
.members = members[0..member_index],
|
|
};
|
|
return try self.spv.resolveType(SpvType.initPayload(&payload.base));
|
|
}
|
|
|
|
const struct_ty = ty.castTag(.@"struct").?.data;
|
|
|
|
if (struct_ty.layout == .Packed) {
|
|
return try self.resolveType(struct_ty.backing_int_ty);
|
|
}
|
|
|
|
const members = try self.spv.arena.alloc(SpvType.Payload.Struct.Member, struct_ty.fields.count());
|
|
var member_index: usize = 0;
|
|
for (struct_ty.fields.values()) |field| {
|
|
if (field.is_comptime or !field.ty.hasRuntimeBits()) continue;
|
|
|
|
members[member_index] = .{
|
|
.ty = try self.resolveType(field.ty),
|
|
.offset = field.offset,
|
|
};
|
|
}
|
|
|
|
const payload = try self.spv.arena.create(SpvType.Payload.Struct);
|
|
payload.* = .{
|
|
.members = members[0..member_index],
|
|
};
|
|
return try self.spv.resolveType(SpvType.initPayload(&payload.base));
|
|
},
|
|
.Null,
|
|
.Undefined,
|
|
.EnumLiteral,
|
|
.ComptimeFloat,
|
|
.ComptimeInt,
|
|
.Type,
|
|
=> unreachable, // Must be comptime.
|
|
|
|
else => |tag| return self.todo("Implement zig type '{}'", .{tag}),
|
|
}
|
|
}
|
|
|
|
fn spirvStorageClass(as: std.builtin.AddressSpace) spec.StorageClass {
|
|
return switch (as) {
|
|
.generic => .Generic, // TODO: Disallow?
|
|
.gs, .fs, .ss => unreachable,
|
|
.shared => .Workgroup,
|
|
.local => .Private,
|
|
.global, .param, .constant, .flash, .flash1, .flash2, .flash3, .flash4, .flash5 => unreachable,
|
|
};
|
|
}
|
|
|
|
fn genDecl(self: *DeclGen) !void {
|
|
const result_id = self.ids.get(self.decl_index).?;
|
|
const decl = self.module.declPtr(self.decl_index);
|
|
|
|
if (decl.val.castTag(.function)) |_| {
|
|
assert(decl.ty.zigTypeTag() == .Fn);
|
|
const prototype_id = try self.resolveTypeId(decl.ty);
|
|
try self.func.prologue.emit(self.spv.gpa, .OpFunction, .{
|
|
.id_result_type = try self.resolveTypeId(decl.ty.fnReturnType()),
|
|
.id_result = result_id,
|
|
.function_control = .{}, // TODO: We can set inline here if the type requires it.
|
|
.function_type = prototype_id.toRef(),
|
|
});
|
|
|
|
const params = decl.ty.fnParamLen();
|
|
var i: usize = 0;
|
|
|
|
try self.args.ensureUnusedCapacity(self.gpa, params);
|
|
while (i < params) : (i += 1) {
|
|
const param_type_id = try self.resolveTypeId(decl.ty.fnParamType(i));
|
|
const arg_result_id = self.spv.allocId();
|
|
try self.func.prologue.emit(self.spv.gpa, .OpFunctionParameter, .{
|
|
.id_result_type = param_type_id,
|
|
.id_result = arg_result_id,
|
|
});
|
|
self.args.appendAssumeCapacity(arg_result_id.toRef());
|
|
}
|
|
|
|
// TODO: This could probably be done in a better way...
|
|
const root_block_id = self.spv.allocId();
|
|
|
|
// The root block of a function declaration should appear before OpVariable instructions,
|
|
// so it is generated into the function's prologue.
|
|
try self.func.prologue.emit(self.spv.gpa, .OpLabel, .{
|
|
.id_result = root_block_id,
|
|
});
|
|
self.current_block_label_id = root_block_id.toRef();
|
|
|
|
const main_body = self.air.getMainBody();
|
|
try self.genBody(main_body);
|
|
|
|
// Append the actual code into the functions section.
|
|
try self.func.body.emit(self.spv.gpa, .OpFunctionEnd, {});
|
|
try self.spv.addFunction(self.func);
|
|
} else {
|
|
// TODO
|
|
// return self.todo("generate decl type {}", .{decl.ty.zigTypeTag()});
|
|
}
|
|
}
|
|
|
|
fn genBody(self: *DeclGen, body: []const Air.Inst.Index) Error!void {
|
|
for (body) |inst| {
|
|
try self.genInst(inst);
|
|
}
|
|
}
|
|
|
|
fn genInst(self: *DeclGen, inst: Air.Inst.Index) !void {
|
|
const air_tags = self.air.instructions.items(.tag);
|
|
const maybe_result_id: ?IdRef = switch (air_tags[inst]) {
|
|
// zig fmt: off
|
|
.add, .addwrap => try self.airArithOp(inst, .OpFAdd, .OpIAdd, .OpIAdd),
|
|
.sub, .subwrap => try self.airArithOp(inst, .OpFSub, .OpISub, .OpISub),
|
|
.mul, .mulwrap => try self.airArithOp(inst, .OpFMul, .OpIMul, .OpIMul),
|
|
|
|
.add_with_overflow => try self.airOverflowArithOp(inst),
|
|
|
|
.shuffle => try self.airShuffle(inst),
|
|
|
|
.bit_and => try self.airBinOpSimple(inst, .OpBitwiseAnd),
|
|
.bit_or => try self.airBinOpSimple(inst, .OpBitwiseOr),
|
|
.xor => try self.airBinOpSimple(inst, .OpBitwiseXor),
|
|
.bool_and => try self.airBinOpSimple(inst, .OpLogicalAnd),
|
|
.bool_or => try self.airBinOpSimple(inst, .OpLogicalOr),
|
|
|
|
.bitcast => try self.airBitcast(inst),
|
|
.not => try self.airNot(inst),
|
|
|
|
.slice_ptr => try self.airSliceField(inst, 0),
|
|
.slice_len => try self.airSliceField(inst, 1),
|
|
.slice_elem_ptr => try self.airSliceElemPtr(inst),
|
|
.slice_elem_val => try self.airSliceElemVal(inst),
|
|
|
|
.cmp_eq => try self.airCmp(inst, .OpFOrdEqual, .OpLogicalEqual, .OpIEqual),
|
|
.cmp_neq => try self.airCmp(inst, .OpFOrdNotEqual, .OpLogicalNotEqual, .OpINotEqual),
|
|
.cmp_gt => try self.airCmp(inst, .OpFOrdGreaterThan, .OpSGreaterThan, .OpUGreaterThan),
|
|
.cmp_gte => try self.airCmp(inst, .OpFOrdGreaterThanEqual, .OpSGreaterThanEqual, .OpUGreaterThanEqual),
|
|
.cmp_lt => try self.airCmp(inst, .OpFOrdLessThan, .OpSLessThan, .OpULessThan),
|
|
.cmp_lte => try self.airCmp(inst, .OpFOrdLessThanEqual, .OpSLessThanEqual, .OpULessThanEqual),
|
|
|
|
.arg => self.airArg(),
|
|
.alloc => try self.airAlloc(inst),
|
|
.block => try self.airBlock(inst),
|
|
.load => try self.airLoad(inst),
|
|
|
|
.br => return self.airBr(inst),
|
|
.breakpoint => return,
|
|
.cond_br => return self.airCondBr(inst),
|
|
.constant => unreachable,
|
|
.dbg_stmt => return self.airDbgStmt(inst),
|
|
.loop => return self.airLoop(inst),
|
|
.ret => return self.airRet(inst),
|
|
.store => return self.airStore(inst),
|
|
.unreach => return self.airUnreach(),
|
|
|
|
.assembly => try self.airAssembly(inst),
|
|
|
|
.call => try self.airCall(inst, .auto),
|
|
.call_always_tail => try self.airCall(inst, .always_tail),
|
|
.call_never_tail => try self.airCall(inst, .never_tail),
|
|
.call_never_inline => try self.airCall(inst, .never_inline),
|
|
|
|
.dbg_var_ptr => return,
|
|
.dbg_var_val => return,
|
|
.dbg_block_begin => return,
|
|
.dbg_block_end => return,
|
|
// zig fmt: on
|
|
|
|
else => |tag| return self.todo("implement AIR tag {s}", .{@tagName(tag)}),
|
|
};
|
|
|
|
const result_id = maybe_result_id orelse return;
|
|
try self.inst_results.putNoClobber(self.gpa, inst, result_id);
|
|
}
|
|
|
|
fn airBinOpSimple(self: *DeclGen, inst: Air.Inst.Index, comptime opcode: Opcode) !?IdRef {
|
|
if (self.liveness.isUnused(inst)) return null;
|
|
const bin_op = self.air.instructions.items(.data)[inst].bin_op;
|
|
const lhs_id = try self.resolve(bin_op.lhs);
|
|
const rhs_id = try self.resolve(bin_op.rhs);
|
|
const result_id = self.spv.allocId();
|
|
const result_type_id = try self.resolveTypeId(self.air.typeOfIndex(inst));
|
|
try self.func.body.emit(self.spv.gpa, opcode, .{
|
|
.id_result_type = result_type_id,
|
|
.id_result = result_id,
|
|
.operand_1 = lhs_id,
|
|
.operand_2 = rhs_id,
|
|
});
|
|
return result_id.toRef();
|
|
}
|
|
|
|
fn airArithOp(
|
|
self: *DeclGen,
|
|
inst: Air.Inst.Index,
|
|
comptime fop: Opcode,
|
|
comptime sop: Opcode,
|
|
comptime uop: Opcode,
|
|
) !?IdRef {
|
|
if (self.liveness.isUnused(inst)) return null;
|
|
// LHS and RHS are guaranteed to have the same type, and AIR guarantees
|
|
// the result to be the same as the LHS and RHS, which matches SPIR-V.
|
|
const ty = self.air.typeOfIndex(inst);
|
|
const bin_op = self.air.instructions.items(.data)[inst].bin_op;
|
|
const lhs_id = try self.resolve(bin_op.lhs);
|
|
const rhs_id = try self.resolve(bin_op.rhs);
|
|
|
|
const result_id = self.spv.allocId();
|
|
const result_type_id = try self.resolveTypeId(ty);
|
|
|
|
assert(self.air.typeOf(bin_op.lhs).eql(ty, self.module));
|
|
assert(self.air.typeOf(bin_op.rhs).eql(ty, self.module));
|
|
|
|
// Binary operations are generally applicable to both scalar and vector operations
|
|
// in SPIR-V, but int and float versions of operations require different opcodes.
|
|
const info = try self.arithmeticTypeInfo(ty);
|
|
|
|
const opcode_index: usize = switch (info.class) {
|
|
.composite_integer => {
|
|
return self.todo("binary operations for composite integers", .{});
|
|
},
|
|
.strange_integer => {
|
|
return self.todo("binary operations for strange integers", .{});
|
|
},
|
|
.integer => switch (info.signedness) {
|
|
.signed => @as(usize, 1),
|
|
.unsigned => @as(usize, 2),
|
|
},
|
|
.float => 0,
|
|
else => unreachable,
|
|
};
|
|
|
|
const operands = .{
|
|
.id_result_type = result_type_id,
|
|
.id_result = result_id,
|
|
.operand_1 = lhs_id,
|
|
.operand_2 = rhs_id,
|
|
};
|
|
|
|
switch (opcode_index) {
|
|
0 => try self.func.body.emit(self.spv.gpa, fop, operands),
|
|
1 => try self.func.body.emit(self.spv.gpa, sop, operands),
|
|
2 => try self.func.body.emit(self.spv.gpa, uop, operands),
|
|
else => unreachable,
|
|
}
|
|
// TODO: Trap on overflow? Probably going to be annoying.
|
|
// TODO: Look into SPV_KHR_no_integer_wrap_decoration which provides NoSignedWrap/NoUnsignedWrap.
|
|
|
|
return result_id.toRef();
|
|
}
|
|
|
|
fn airOverflowArithOp(self: *DeclGen, inst: Air.Inst.Index) !?IdRef {
|
|
if (self.liveness.isUnused(inst)) return null;
|
|
|
|
const target = self.getTarget();
|
|
|
|
const ty_pl = self.air.instructions.items(.data)[inst].ty_pl;
|
|
const extra = self.air.extraData(Air.Bin, ty_pl.payload).data;
|
|
const lhs = try self.resolve(extra.lhs);
|
|
const rhs = try self.resolve(extra.rhs);
|
|
|
|
const operand_ty = self.air.typeOf(extra.lhs);
|
|
const result_ty = self.air.typeOfIndex(inst);
|
|
|
|
const operand_ty_id = try self.resolveTypeId(operand_ty);
|
|
const result_type_id = try self.resolveTypeId(result_ty);
|
|
|
|
const operand_bits = operand_ty.intInfo(target).bits;
|
|
const overflow_member_ty = try self.intType(.unsigned, operand_bits);
|
|
const overflow_member_ty_id = self.spv.typeResultId(overflow_member_ty);
|
|
|
|
const op_result_id = blk: {
|
|
// Construct the SPIR-V result type.
|
|
// It is almost the same as the zig one, except that the fields must be the same type
|
|
// and they must be unsigned.
|
|
const overflow_result_ty = try self.simpleStructTypeId(&.{
|
|
.{ .ty = overflow_member_ty, .offset = 0 },
|
|
.{ .ty = overflow_member_ty, .offset = @intCast(u32, operand_ty.abiSize(target)) },
|
|
});
|
|
const result_id = self.spv.allocId();
|
|
try self.func.body.emit(self.spv.gpa, .OpIAddCarry, .{
|
|
.id_result_type = overflow_result_ty,
|
|
.id_result = result_id,
|
|
.operand_1 = lhs,
|
|
.operand_2 = rhs,
|
|
});
|
|
break :blk result_id.toRef();
|
|
};
|
|
|
|
// Now convert the SPIR-V flavor result into a Zig-flavor result.
|
|
// First, extract the two fields.
|
|
const unsigned_result = try self.extractField(overflow_member_ty_id, op_result_id, 0);
|
|
const overflow = try self.extractField(overflow_member_ty_id, op_result_id, 0);
|
|
|
|
// We need to convert the results to the types that Zig expects here.
|
|
// The `result` is the same type except unsigned, so we can just bitcast that.
|
|
const result = try self.bitcast(operand_ty_id, unsigned_result);
|
|
|
|
// The overflow needs to be converted into whatever is used to represent it in Zig.
|
|
const casted_overflow = blk: {
|
|
const ov_ty = result_ty.tupleFields().types[1];
|
|
const ov_ty_id = try self.resolveTypeId(ov_ty);
|
|
const result_id = self.spv.allocId();
|
|
try self.func.body.emit(self.spv.gpa, .OpUConvert, .{
|
|
.id_result_type = ov_ty_id,
|
|
.id_result = result_id,
|
|
.unsigned_value = overflow,
|
|
});
|
|
break :blk result_id.toRef();
|
|
};
|
|
|
|
// TODO: If copying this function for borrow, make sure to convert -1 to 1 as appropriate.
|
|
|
|
// Finally, construct the Zig type.
|
|
// Layout is result, overflow.
|
|
const result_id = self.spv.allocId();
|
|
try self.func.body.emit(self.spv.gpa, .OpCompositeConstruct, .{
|
|
.id_result_type = result_type_id,
|
|
.id_result = result_id,
|
|
.constituents = &.{
|
|
result,
|
|
casted_overflow,
|
|
},
|
|
});
|
|
return result_id.toRef();
|
|
}
|
|
|
|
fn airShuffle(self: *DeclGen, inst: Air.Inst.Index) !?IdRef {
|
|
if (self.liveness.isUnused(inst)) return null;
|
|
const ty = self.air.typeOfIndex(inst);
|
|
const ty_pl = self.air.instructions.items(.data)[inst].ty_pl;
|
|
const extra = self.air.extraData(Air.Shuffle, ty_pl.payload).data;
|
|
const a = try self.resolve(extra.a);
|
|
const b = try self.resolve(extra.b);
|
|
const mask = self.air.values[extra.mask];
|
|
const mask_len = extra.mask_len;
|
|
const a_len = self.air.typeOf(extra.a).vectorLen();
|
|
|
|
const result_id = self.spv.allocId();
|
|
const result_type_id = try self.resolveTypeId(ty);
|
|
// Similar to LLVM, SPIR-V uses indices larger than the length of the first vector
|
|
// to index into the second vector.
|
|
try self.func.body.emitRaw(self.spv.gpa, .OpVectorShuffle, 4 + mask_len);
|
|
self.func.body.writeOperand(spec.IdResultType, result_type_id);
|
|
self.func.body.writeOperand(spec.IdResult, result_id);
|
|
self.func.body.writeOperand(spec.IdRef, a);
|
|
self.func.body.writeOperand(spec.IdRef, b);
|
|
|
|
var i: usize = 0;
|
|
while (i < mask_len) : (i += 1) {
|
|
var buf: Value.ElemValueBuffer = undefined;
|
|
const elem = mask.elemValueBuffer(self.module, i, &buf);
|
|
if (elem.isUndef()) {
|
|
self.func.body.writeOperand(spec.LiteralInteger, 0xFFFF_FFFF);
|
|
} else {
|
|
const int = elem.toSignedInt(self.getTarget());
|
|
const unsigned = if (int >= 0) @intCast(u32, int) else @intCast(u32, ~int + a_len);
|
|
self.func.body.writeOperand(spec.LiteralInteger, unsigned);
|
|
}
|
|
}
|
|
return result_id.toRef();
|
|
}
|
|
|
|
fn airCmp(self: *DeclGen, inst: Air.Inst.Index, comptime fop: Opcode, comptime sop: Opcode, comptime uop: Opcode) !?IdRef {
|
|
if (self.liveness.isUnused(inst)) return null;
|
|
const bin_op = self.air.instructions.items(.data)[inst].bin_op;
|
|
const lhs_id = try self.resolve(bin_op.lhs);
|
|
const rhs_id = try self.resolve(bin_op.rhs);
|
|
const result_id = self.spv.allocId();
|
|
const result_type_id = try self.resolveTypeId(Type.initTag(.bool));
|
|
const op_ty = self.air.typeOf(bin_op.lhs);
|
|
assert(op_ty.eql(self.air.typeOf(bin_op.rhs), self.module));
|
|
|
|
// Comparisons are generally applicable to both scalar and vector operations in SPIR-V,
|
|
// but int and float versions of operations require different opcodes.
|
|
const info = try self.arithmeticTypeInfo(op_ty);
|
|
|
|
const opcode_index: usize = switch (info.class) {
|
|
.composite_integer => {
|
|
return self.todo("binary operations for composite integers", .{});
|
|
},
|
|
.strange_integer => {
|
|
return self.todo("comparison for strange integers", .{});
|
|
},
|
|
.float => 0,
|
|
.bool => 1,
|
|
.integer => switch (info.signedness) {
|
|
.signed => @as(usize, 1),
|
|
.unsigned => @as(usize, 2),
|
|
},
|
|
};
|
|
|
|
const operands = .{
|
|
.id_result_type = result_type_id,
|
|
.id_result = result_id,
|
|
.operand_1 = lhs_id,
|
|
.operand_2 = rhs_id,
|
|
};
|
|
|
|
switch (opcode_index) {
|
|
0 => try self.func.body.emit(self.spv.gpa, fop, operands),
|
|
1 => try self.func.body.emit(self.spv.gpa, sop, operands),
|
|
2 => try self.func.body.emit(self.spv.gpa, uop, operands),
|
|
else => unreachable,
|
|
}
|
|
|
|
return result_id.toRef();
|
|
}
|
|
|
|
fn bitcast(self: *DeclGen, target_type_id: IdResultType, value_id: IdRef) !IdRef {
|
|
const result_id = self.spv.allocId();
|
|
try self.func.body.emit(self.spv.gpa, .OpBitcast, .{
|
|
.id_result_type = target_type_id,
|
|
.id_result = result_id,
|
|
.operand = value_id,
|
|
});
|
|
return result_id.toRef();
|
|
}
|
|
|
|
fn airBitcast(self: *DeclGen, inst: Air.Inst.Index) !?IdRef {
|
|
if (self.liveness.isUnused(inst)) return null;
|
|
const ty_op = self.air.instructions.items(.data)[inst].ty_op;
|
|
const operand_id = try self.resolve(ty_op.operand);
|
|
const result_type_id = try self.resolveTypeId(self.air.typeOfIndex(inst));
|
|
return try self.bitcast(result_type_id, operand_id);
|
|
}
|
|
|
|
fn airNot(self: *DeclGen, inst: Air.Inst.Index) !?IdRef {
|
|
if (self.liveness.isUnused(inst)) return null;
|
|
const ty_op = self.air.instructions.items(.data)[inst].ty_op;
|
|
const operand_id = try self.resolve(ty_op.operand);
|
|
const result_id = self.spv.allocId();
|
|
const result_type_id = try self.resolveTypeId(Type.initTag(.bool));
|
|
try self.func.body.emit(self.spv.gpa, .OpLogicalNot, .{
|
|
.id_result_type = result_type_id,
|
|
.id_result = result_id,
|
|
.operand = operand_id,
|
|
});
|
|
return result_id.toRef();
|
|
}
|
|
|
|
fn extractField(self: *DeclGen, result_ty: IdResultType, object: IdRef, field: u32) !IdRef {
|
|
const result_id = self.spv.allocId();
|
|
try self.func.body.emit(self.spv.gpa, .OpCompositeExtract, .{
|
|
.id_result_type = result_ty,
|
|
.id_result = result_id,
|
|
.composite = object,
|
|
.indexes = &.{field},
|
|
});
|
|
return result_id.toRef();
|
|
}
|
|
|
|
fn airSliceField(self: *DeclGen, inst: Air.Inst.Index, field: u32) !?IdRef {
|
|
if (self.liveness.isUnused(inst)) return null;
|
|
const ty_op = self.air.instructions.items(.data)[inst].ty_op;
|
|
return try self.extractField(
|
|
try self.resolveTypeId(self.air.typeOfIndex(inst)),
|
|
try self.resolve(ty_op.operand),
|
|
field,
|
|
);
|
|
}
|
|
|
|
fn airSliceElemPtr(self: *DeclGen, inst: Air.Inst.Index) !?IdRef {
|
|
const bin_op = self.air.instructions.items(.data)[inst].bin_op;
|
|
const slice_ty = self.air.typeOf(bin_op.lhs);
|
|
if (!slice_ty.isVolatilePtr() and self.liveness.isUnused(inst)) return null;
|
|
|
|
const slice = try self.resolve(bin_op.lhs);
|
|
const index = try self.resolve(bin_op.rhs);
|
|
|
|
const spv_ptr_ty = try self.resolveTypeId(self.air.typeOfIndex(inst));
|
|
|
|
const slice_ptr = blk: {
|
|
const result_id = self.spv.allocId();
|
|
try self.func.body.emit(self.spv.gpa, .OpCompositeExtract, .{
|
|
.id_result_type = spv_ptr_ty,
|
|
.id_result = result_id,
|
|
.composite = slice,
|
|
.indexes = &.{0},
|
|
});
|
|
break :blk result_id.toRef();
|
|
};
|
|
|
|
const result_id = self.spv.allocId();
|
|
try self.func.body.emit(self.spv.gpa, .OpInBoundsAccessChain, .{
|
|
.id_result_type = spv_ptr_ty,
|
|
.id_result = result_id,
|
|
.base = slice_ptr,
|
|
.indexes = &.{index},
|
|
});
|
|
return result_id.toRef();
|
|
}
|
|
|
|
fn airSliceElemVal(self: *DeclGen, inst: Air.Inst.Index) !?IdRef {
|
|
const bin_op = self.air.instructions.items(.data)[inst].bin_op;
|
|
const slice_ty = self.air.typeOf(bin_op.lhs);
|
|
if (!slice_ty.isVolatilePtr() and self.liveness.isUnused(inst)) return null;
|
|
|
|
const slice = try self.resolve(bin_op.lhs);
|
|
const index = try self.resolve(bin_op.rhs);
|
|
|
|
const spv_elem_ty = try self.resolveTypeId(self.air.typeOfIndex(inst));
|
|
var slice_buf: Type.SlicePtrFieldTypeBuffer = undefined;
|
|
const spv_ptr_ty = try self.resolveTypeId(slice_ty.slicePtrFieldType(&slice_buf));
|
|
|
|
const slice_ptr = blk: {
|
|
const result_id = self.spv.allocId();
|
|
try self.func.body.emit(self.spv.gpa, .OpCompositeExtract, .{
|
|
.id_result_type = spv_ptr_ty,
|
|
.id_result = result_id,
|
|
.composite = slice,
|
|
.indexes = &.{0},
|
|
});
|
|
break :blk result_id.toRef();
|
|
};
|
|
|
|
const elem_ptr = blk: {
|
|
const result_id = self.spv.allocId();
|
|
try self.func.body.emit(self.spv.gpa, .OpInBoundsAccessChain, .{
|
|
.id_result_type = spv_ptr_ty,
|
|
.id_result = result_id,
|
|
.base = slice_ptr,
|
|
.indexes = &.{index},
|
|
});
|
|
break :blk result_id.toRef();
|
|
};
|
|
|
|
const result_id = self.spv.allocId();
|
|
try self.func.body.emit(self.spv.gpa, .OpLoad, .{
|
|
.id_result_type = spv_elem_ty,
|
|
.id_result = result_id,
|
|
.pointer = elem_ptr,
|
|
});
|
|
return result_id.toRef();
|
|
}
|
|
|
|
fn airAlloc(self: *DeclGen, inst: Air.Inst.Index) !?IdRef {
|
|
if (self.liveness.isUnused(inst)) return null;
|
|
const ty = self.air.typeOfIndex(inst);
|
|
const result_type_id = try self.resolveTypeId(ty);
|
|
const result_id = self.spv.allocId();
|
|
|
|
// Rather than generating into code here, we're just going to generate directly into the functions section so that
|
|
// variable declarations appear in the first block of the function.
|
|
const storage_class = spirvStorageClass(ty.ptrAddressSpace());
|
|
const section = if (storage_class == .Function)
|
|
&self.func.prologue
|
|
else
|
|
&self.spv.sections.types_globals_constants;
|
|
|
|
try section.emit(self.spv.gpa, .OpVariable, .{
|
|
.id_result_type = result_type_id,
|
|
.id_result = result_id,
|
|
.storage_class = storage_class,
|
|
});
|
|
return result_id.toRef();
|
|
}
|
|
|
|
fn airArg(self: *DeclGen) IdRef {
|
|
defer self.next_arg_index += 1;
|
|
return self.args.items[self.next_arg_index];
|
|
}
|
|
|
|
fn airBlock(self: *DeclGen, inst: Air.Inst.Index) !?IdRef {
|
|
// In AIR, a block doesn't really define an entry point like a block, but more like a scope that breaks can jump out of and
|
|
// "return" a value from. This cannot be directly modelled in SPIR-V, so in a block instruction, we're going to split up
|
|
// the current block by first generating the code of the block, then a label, and then generate the rest of the current
|
|
// ir.Block in a different SPIR-V block.
|
|
|
|
const label_id = self.spv.allocId();
|
|
|
|
// 4 chosen as arbitrary initial capacity.
|
|
var incoming_blocks = try std.ArrayListUnmanaged(IncomingBlock).initCapacity(self.gpa, 4);
|
|
|
|
try self.blocks.putNoClobber(self.gpa, inst, .{
|
|
.label_id = label_id.toRef(),
|
|
.incoming_blocks = &incoming_blocks,
|
|
});
|
|
defer {
|
|
assert(self.blocks.remove(inst));
|
|
incoming_blocks.deinit(self.gpa);
|
|
}
|
|
|
|
const ty = self.air.typeOfIndex(inst);
|
|
const inst_datas = self.air.instructions.items(.data);
|
|
const extra = self.air.extraData(Air.Block, inst_datas[inst].ty_pl.payload);
|
|
const body = self.air.extra[extra.end..][0..extra.data.body_len];
|
|
|
|
try self.genBody(body);
|
|
try self.beginSpvBlock(label_id);
|
|
|
|
// If this block didn't produce a value, simply return here.
|
|
if (!ty.hasRuntimeBitsIgnoreComptime())
|
|
return null;
|
|
|
|
// Combine the result from the blocks using the Phi instruction.
|
|
|
|
const result_id = self.spv.allocId();
|
|
|
|
// TODO: OpPhi is limited in the types that it may produce, such as pointers. Figure out which other types
|
|
// are not allowed to be created from a phi node, and throw an error for those.
|
|
const result_type_id = try self.resolveTypeId(ty);
|
|
_ = result_type_id;
|
|
|
|
try self.func.body.emitRaw(self.spv.gpa, .OpPhi, 2 + @intCast(u16, incoming_blocks.items.len * 2)); // result type + result + variable/parent...
|
|
|
|
for (incoming_blocks.items) |incoming| {
|
|
self.func.body.writeOperand(spec.PairIdRefIdRef, .{ incoming.break_value_id, incoming.src_label_id });
|
|
}
|
|
|
|
return result_id.toRef();
|
|
}
|
|
|
|
fn airBr(self: *DeclGen, inst: Air.Inst.Index) !void {
|
|
const br = self.air.instructions.items(.data)[inst].br;
|
|
const block = self.blocks.get(br.block_inst).?;
|
|
const operand_ty = self.air.typeOf(br.operand);
|
|
|
|
if (operand_ty.hasRuntimeBits()) {
|
|
const operand_id = try self.resolve(br.operand);
|
|
// current_block_label_id should not be undefined here, lest there is a br or br_void in the function's body.
|
|
try block.incoming_blocks.append(self.gpa, .{ .src_label_id = self.current_block_label_id, .break_value_id = operand_id });
|
|
}
|
|
|
|
try self.func.body.emit(self.spv.gpa, .OpBranch, .{ .target_label = block.label_id });
|
|
}
|
|
|
|
fn airCondBr(self: *DeclGen, inst: Air.Inst.Index) !void {
|
|
const pl_op = self.air.instructions.items(.data)[inst].pl_op;
|
|
const cond_br = self.air.extraData(Air.CondBr, pl_op.payload);
|
|
const then_body = self.air.extra[cond_br.end..][0..cond_br.data.then_body_len];
|
|
const else_body = self.air.extra[cond_br.end + then_body.len ..][0..cond_br.data.else_body_len];
|
|
const condition_id = try self.resolve(pl_op.operand);
|
|
|
|
// These will always generate a new SPIR-V block, since they are ir.Body and not ir.Block.
|
|
const then_label_id = self.spv.allocId();
|
|
const else_label_id = self.spv.allocId();
|
|
|
|
// TODO: We can generate OpSelectionMerge here if we know the target block that both of these will resolve to,
|
|
// but i don't know if those will always resolve to the same block.
|
|
|
|
try self.func.body.emit(self.spv.gpa, .OpBranchConditional, .{
|
|
.condition = condition_id,
|
|
.true_label = then_label_id.toRef(),
|
|
.false_label = else_label_id.toRef(),
|
|
});
|
|
|
|
try self.beginSpvBlock(then_label_id);
|
|
try self.genBody(then_body);
|
|
try self.beginSpvBlock(else_label_id);
|
|
try self.genBody(else_body);
|
|
}
|
|
|
|
fn airDbgStmt(self: *DeclGen, inst: Air.Inst.Index) !void {
|
|
const dbg_stmt = self.air.instructions.items(.data)[inst].dbg_stmt;
|
|
const src_fname_id = try self.spv.resolveSourceFileName(self.module.declPtr(self.decl_index));
|
|
try self.func.body.emit(self.spv.gpa, .OpLine, .{
|
|
.file = src_fname_id,
|
|
.line = dbg_stmt.line,
|
|
.column = dbg_stmt.column,
|
|
});
|
|
}
|
|
|
|
fn airLoad(self: *DeclGen, inst: Air.Inst.Index) !IdRef {
|
|
const ty_op = self.air.instructions.items(.data)[inst].ty_op;
|
|
const operand_id = try self.resolve(ty_op.operand);
|
|
const ty = self.air.typeOfIndex(inst);
|
|
|
|
const result_type_id = try self.resolveTypeId(ty);
|
|
const result_id = self.spv.allocId();
|
|
|
|
const access = spec.MemoryAccess.Extended{
|
|
.Volatile = ty.isVolatilePtr(),
|
|
};
|
|
|
|
try self.func.body.emit(self.spv.gpa, .OpLoad, .{
|
|
.id_result_type = result_type_id,
|
|
.id_result = result_id,
|
|
.pointer = operand_id,
|
|
.memory_access = access,
|
|
});
|
|
|
|
return result_id.toRef();
|
|
}
|
|
|
|
fn airLoop(self: *DeclGen, inst: Air.Inst.Index) !void {
|
|
const ty_pl = self.air.instructions.items(.data)[inst].ty_pl;
|
|
const loop = self.air.extraData(Air.Block, ty_pl.payload);
|
|
const body = self.air.extra[loop.end..][0..loop.data.body_len];
|
|
const loop_label_id = self.spv.allocId();
|
|
|
|
// Jump to the loop entry point
|
|
try self.func.body.emit(self.spv.gpa, .OpBranch, .{ .target_label = loop_label_id.toRef() });
|
|
|
|
// TODO: Look into OpLoopMerge.
|
|
try self.beginSpvBlock(loop_label_id);
|
|
try self.genBody(body);
|
|
|
|
try self.func.body.emit(self.spv.gpa, .OpBranch, .{ .target_label = loop_label_id.toRef() });
|
|
}
|
|
|
|
fn airRet(self: *DeclGen, inst: Air.Inst.Index) !void {
|
|
if (self.liveness.isUnused(inst)) return;
|
|
const operand = self.air.instructions.items(.data)[inst].un_op;
|
|
const operand_ty = self.air.typeOf(operand);
|
|
if (operand_ty.hasRuntimeBits()) {
|
|
const operand_id = try self.resolve(operand);
|
|
try self.func.body.emit(self.spv.gpa, .OpReturnValue, .{ .value = operand_id });
|
|
} else {
|
|
try self.func.body.emit(self.spv.gpa, .OpReturn, {});
|
|
}
|
|
}
|
|
|
|
fn airStore(self: *DeclGen, inst: Air.Inst.Index) !void {
|
|
const bin_op = self.air.instructions.items(.data)[inst].bin_op;
|
|
const dst_ptr_id = try self.resolve(bin_op.lhs);
|
|
const src_val_id = try self.resolve(bin_op.rhs);
|
|
const lhs_ty = self.air.typeOf(bin_op.lhs);
|
|
|
|
const access = spec.MemoryAccess.Extended{
|
|
.Volatile = lhs_ty.isVolatilePtr(),
|
|
};
|
|
|
|
try self.func.body.emit(self.spv.gpa, .OpStore, .{
|
|
.pointer = dst_ptr_id,
|
|
.object = src_val_id,
|
|
.memory_access = access,
|
|
});
|
|
}
|
|
|
|
fn airUnreach(self: *DeclGen) !void {
|
|
try self.func.body.emit(self.spv.gpa, .OpUnreachable, {});
|
|
}
|
|
|
|
fn airAssembly(self: *DeclGen, inst: Air.Inst.Index) !?IdRef {
|
|
const ty_pl = self.air.instructions.items(.data)[inst].ty_pl;
|
|
const extra = self.air.extraData(Air.Asm, ty_pl.payload);
|
|
|
|
const is_volatile = @truncate(u1, extra.data.flags >> 31) != 0;
|
|
const clobbers_len = @truncate(u31, extra.data.flags);
|
|
|
|
if (!is_volatile and self.liveness.isUnused(inst)) return null;
|
|
|
|
var extra_i: usize = extra.end;
|
|
const outputs = @ptrCast([]const Air.Inst.Ref, self.air.extra[extra_i..][0..extra.data.outputs_len]);
|
|
extra_i += outputs.len;
|
|
const inputs = @ptrCast([]const Air.Inst.Ref, self.air.extra[extra_i..][0..extra.data.inputs_len]);
|
|
extra_i += inputs.len;
|
|
|
|
if (outputs.len > 1) {
|
|
return self.todo("implement inline asm with more than 1 output", .{});
|
|
}
|
|
|
|
var output_extra_i = extra_i;
|
|
for (outputs) |output| {
|
|
if (output != .none) {
|
|
return self.todo("implement inline asm with non-returned output", .{});
|
|
}
|
|
const extra_bytes = std.mem.sliceAsBytes(self.air.extra[extra_i..]);
|
|
const constraint = std.mem.sliceTo(std.mem.sliceAsBytes(self.air.extra[extra_i..]), 0);
|
|
const name = std.mem.sliceTo(extra_bytes[constraint.len + 1 ..], 0);
|
|
extra_i += (constraint.len + name.len + (2 + 3)) / 4;
|
|
// TODO: Record output and use it somewhere.
|
|
}
|
|
|
|
var input_extra_i = extra_i;
|
|
for (inputs) |input| {
|
|
const extra_bytes = std.mem.sliceAsBytes(self.air.extra[extra_i..]);
|
|
const constraint = std.mem.sliceTo(extra_bytes, 0);
|
|
const name = std.mem.sliceTo(extra_bytes[constraint.len + 1 ..], 0);
|
|
// This equation accounts for the fact that even if we have exactly 4 bytes
|
|
// for the string, we still use the next u32 for the null terminator.
|
|
extra_i += (constraint.len + name.len + (2 + 3)) / 4;
|
|
// TODO: Record input and use it somewhere.
|
|
_ = input;
|
|
}
|
|
|
|
{
|
|
var clobber_i: u32 = 0;
|
|
while (clobber_i < clobbers_len) : (clobber_i += 1) {
|
|
const clobber = std.mem.sliceTo(std.mem.sliceAsBytes(self.air.extra[extra_i..]), 0);
|
|
extra_i += clobber.len / 4 + 1;
|
|
// TODO: Record clobber and use it somewhere.
|
|
}
|
|
}
|
|
|
|
const asm_source = std.mem.sliceAsBytes(self.air.extra[extra_i..])[0..extra.data.source_len];
|
|
|
|
var as = SpvAssembler{
|
|
.gpa = self.gpa,
|
|
.src = asm_source,
|
|
.spv = self.spv,
|
|
.func = &self.func,
|
|
};
|
|
defer as.deinit();
|
|
|
|
for (inputs) |input| {
|
|
const extra_bytes = std.mem.sliceAsBytes(self.air.extra[input_extra_i..]);
|
|
const constraint = std.mem.sliceTo(extra_bytes, 0);
|
|
const name = std.mem.sliceTo(extra_bytes[constraint.len + 1 ..], 0);
|
|
// This equation accounts for the fact that even if we have exactly 4 bytes
|
|
// for the string, we still use the next u32 for the null terminator.
|
|
input_extra_i += (constraint.len + name.len + (2 + 3)) / 4;
|
|
|
|
const value = try self.resolve(input);
|
|
try as.value_map.put(as.gpa, name, .{ .value = value });
|
|
}
|
|
|
|
as.assemble() catch |err| switch (err) {
|
|
error.AssembleFail => {
|
|
// TODO: For now the compiler only supports a single error message per decl,
|
|
// so to translate the possible multiple errors from the assembler, emit
|
|
// them as notes here.
|
|
// TODO: Translate proper error locations.
|
|
assert(as.errors.items.len != 0);
|
|
assert(self.error_msg == null);
|
|
const loc = LazySrcLoc.nodeOffset(0);
|
|
const src_loc = loc.toSrcLoc(self.module.declPtr(self.decl_index));
|
|
self.error_msg = try Module.ErrorMsg.create(self.module.gpa, src_loc, "failed to assemble SPIR-V inline assembly", .{});
|
|
const notes = try self.module.gpa.alloc(Module.ErrorMsg, as.errors.items.len);
|
|
|
|
// Sub-scope to prevent `return error.CodegenFail` from running the errdefers.
|
|
{
|
|
errdefer self.module.gpa.free(notes);
|
|
var i: usize = 0;
|
|
errdefer for (notes[0..i]) |*note| {
|
|
note.deinit(self.module.gpa);
|
|
};
|
|
|
|
while (i < as.errors.items.len) : (i += 1) {
|
|
notes[i] = try Module.ErrorMsg.init(self.module.gpa, src_loc, "{s}", .{as.errors.items[i].msg});
|
|
}
|
|
}
|
|
self.error_msg.?.notes = notes;
|
|
return error.CodegenFail;
|
|
},
|
|
else => |others| return others,
|
|
};
|
|
|
|
for (outputs) |output| {
|
|
_ = output;
|
|
const extra_bytes = std.mem.sliceAsBytes(self.air.extra[output_extra_i..]);
|
|
const constraint = std.mem.sliceTo(std.mem.sliceAsBytes(self.air.extra[output_extra_i..]), 0);
|
|
const name = std.mem.sliceTo(extra_bytes[constraint.len + 1 ..], 0);
|
|
output_extra_i += (constraint.len + name.len + (2 + 3)) / 4;
|
|
|
|
const result = as.value_map.get(name) orelse return {
|
|
return self.fail("invalid asm output '{s}'", .{name});
|
|
};
|
|
|
|
switch (result) {
|
|
.just_declared, .unresolved_forward_reference => unreachable,
|
|
.ty => return self.fail("cannot return spir-v type as value from assembly", .{}),
|
|
.value => |ref| return ref,
|
|
}
|
|
|
|
// TODO: Multiple results
|
|
}
|
|
|
|
return null;
|
|
}
|
|
|
|
fn airCall(self: *DeclGen, inst: Air.Inst.Index, modifier: std.builtin.CallOptions.Modifier) !?IdRef {
|
|
_ = modifier;
|
|
|
|
const pl_op = self.air.instructions.items(.data)[inst].pl_op;
|
|
const extra = self.air.extraData(Air.Call, pl_op.payload);
|
|
const args = @ptrCast([]const Air.Inst.Ref, self.air.extra[extra.end..][0..extra.data.args_len]);
|
|
const callee_ty = self.air.typeOf(pl_op.operand);
|
|
const zig_fn_ty = switch (callee_ty.zigTypeTag()) {
|
|
.Fn => callee_ty,
|
|
.Pointer => return self.fail("cannot call function pointers", .{}),
|
|
else => unreachable,
|
|
};
|
|
const fn_info = zig_fn_ty.fnInfo();
|
|
const return_type = fn_info.return_type;
|
|
|
|
const result_type_id = try self.resolveTypeId(return_type);
|
|
const result_id = self.spv.allocId();
|
|
const callee_id = try self.resolve(pl_op.operand);
|
|
|
|
try self.func.body.emitRaw(self.spv.gpa, .OpFunctionCall, 3 + args.len);
|
|
self.func.body.writeOperand(spec.IdResultType, result_type_id);
|
|
self.func.body.writeOperand(spec.IdResult, result_id);
|
|
self.func.body.writeOperand(spec.IdRef, callee_id);
|
|
|
|
for (args) |arg| {
|
|
const arg_id = try self.resolve(arg);
|
|
const arg_ty = self.air.typeOf(arg);
|
|
if (!arg_ty.hasRuntimeBitsIgnoreComptime()) continue;
|
|
|
|
self.func.body.writeOperand(spec.IdRef, arg_id);
|
|
}
|
|
|
|
if (return_type.isNoReturn()) {
|
|
try self.func.body.emit(self.spv.gpa, .OpUnreachable, {});
|
|
}
|
|
|
|
if (self.liveness.isUnused(inst) or !return_type.hasRuntimeBitsIgnoreComptime()) {
|
|
return null;
|
|
}
|
|
|
|
return result_id.toRef();
|
|
}
|
|
};
|