mirror of
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synced 2025-12-07 23:03:08 +00:00
d29871977f
We already have a LICENSE file that covers the Zig Standard Library. We no longer need to remind everyone that the license is MIT in every single file. Previously this was introduced to clarify the situation for a fork of Zig that made Zig's LICENSE file harder to find, and replaced it with their own license that required annual payments to their company. However that fork now appears to be dead. So there is no need to reinforce the copyright notice in every single file.
127 lines
3.5 KiB
Zig
127 lines
3.5 KiB
Zig
const std = @import("std");
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const builtin = std.builtin;
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fn __clzsi2_generic(a: i32) callconv(.C) i32 {
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@setRuntimeSafety(builtin.is_test);
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var x = @bitCast(u32, a);
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var n: i32 = 32;
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// Count first bit set using binary search, from Hacker's Delight
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var y: u32 = 0;
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inline for ([_]i32{ 16, 8, 4, 2, 1 }) |shift| {
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y = x >> shift;
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if (y != 0) {
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n = n - shift;
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x = y;
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}
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}
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return n - @bitCast(i32, x);
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}
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fn __clzsi2_thumb1() callconv(.Naked) void {
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@setRuntimeSafety(false);
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// Similar to the generic version with the last two rounds replaced by a LUT
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asm volatile (
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\\ movs r1, #32
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\\ lsrs r2, r0, #16
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\\ beq 1f
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\\ subs r1, #16
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\\ movs r0, r2
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\\ 1:
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\\ lsrs r2, r0, #8
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\\ beq 1f
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\\ subs r1, #8
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\\ movs r0, r2
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\\ 1:
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\\ lsrs r2, r0, #4
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\\ beq 1f
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\\ subs r1, #4
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\\ movs r0, r2
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\\ 1:
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\\ ldr r3, =LUT
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\\ ldrb r0, [r3, r0]
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\\ subs r0, r1, r0
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\\ bx lr
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\\ .p2align 2
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\\ // Number of bits set in the 0-15 range
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\\ LUT:
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\\ .byte 0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4
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);
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unreachable;
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}
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fn __clzsi2_arm32() callconv(.Naked) void {
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@setRuntimeSafety(false);
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asm volatile (
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\\ // Assumption: n != 0
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\\ // r0: n
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\\ // r1: count of leading zeros in n + 1
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\\ // r2: scratch register for shifted r0
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\\ mov r1, #1
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\\
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\\ // Basic block:
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\\ // if ((r0 >> SHIFT) == 0)
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\\ // r1 += SHIFT;
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\\ // else
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\\ // r0 >>= SHIFT;
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\\ // for descending powers of two as SHIFT.
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\\ lsrs r2, r0, #16
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\\ movne r0, r2
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\\ addeq r1, #16
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\\
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\\ lsrs r2, r0, #8
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\\ movne r0, r2
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\\ addeq r1, #8
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\\
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\\ lsrs r2, r0, #4
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\\ movne r0, r2
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\\ addeq r1, #4
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\\
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\\ lsrs r2, r0, #2
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\\ movne r0, r2
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\\ addeq r1, #2
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\\
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\\ // The basic block invariants at this point are (r0 >> 2) == 0 and
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\\ // r0 != 0. This means 1 <= r0 <= 3 and 0 <= (r0 >> 1) <= 1.
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\\ //
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\\ // r0 | (r0 >> 1) == 0 | (r0 >> 1) == 1 | -(r0 >> 1) | 1 - (r0 >> 1)f
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\\ // ---+----------------+----------------+------------+--------------
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\\ // 1 | 1 | 0 | 0 | 1
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\\ // 2 | 0 | 1 | -1 | 0
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\\ // 3 | 0 | 1 | -1 | 0
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\\ //
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\\ // The r1's initial value of 1 compensates for the 1 here.
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\\ sub r0, r1, r0, lsr #1
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\\ bx lr
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);
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unreachable;
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}
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pub const __clzsi2 = impl: {
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switch (std.Target.current.cpu.arch) {
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.arm, .armeb, .thumb, .thumbeb => {
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const use_thumb1 =
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(std.Target.current.cpu.arch.isThumb() or
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std.Target.arm.featureSetHas(std.Target.current.cpu.features, .noarm)) and
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!std.Target.arm.featureSetHas(std.Target.current.cpu.features, .thumb2);
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if (use_thumb1) break :impl __clzsi2_thumb1
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// From here on we're either targeting Thumb2 or ARM.
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else if (!std.Target.current.cpu.arch.isThumb()) break :impl __clzsi2_arm32
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// Use the generic implementation otherwise.
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else break :impl __clzsi2_generic;
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},
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else => break :impl __clzsi2_generic,
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}
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};
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test "test clzsi2" {
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_ = @import("clzsi2_test.zig");
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}
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