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c8ca05e93a
What is `sparcel`, you might ask? Good question! If you take a peek in the SPARC v8 manual, §2.2, it is quite explicit that SPARC v8 is a big-endian architecture. No little-endian or mixed-endian support to be found here. On the other hand, the SPARC v9 manual, in §3.2.1.2, states that it has support for mixed-endian operation, with big-endian mode being the default. Ok, so `sparcel` must just be referring to SPARC v9 running in little-endian mode, surely? Nope: *40b4fd7a3e/llvm/lib/Target/Sparc/SparcTargetMachine.cpp (L226)*40b4fd7a3e/llvm/lib/Target/Sparc/SparcTargetMachine.cpp (L104)So, `sparcel` in LLVM is referring to some sort of fantastical little-endian SPARC v8 architecture. I've scoured the internet and I can find absolutely no evidence that such a thing exists or has ever existed. In fact, I can find no evidence that a little-endian implementation of SPARC v9 ever existed, either. Or any SPARC version, actually! The support was added here: https://reviews.llvm.org/D8741 Notably, there is no mention whatsoever of what CPU this might be referring to, and no justification given for the "but some are little" comment added in the patch. My best guess is that this might have been some private exercise in creating a little-endian version of SPARC that never saw the light of day. Given that SPARC v8 explicitly doesn't support little-endian operation (let alone little-endian instruction encoding!), and no CPU is known to be implemented as such, I think it's very reasonable for us to just remove this support.
56 lines
1.3 KiB
Zig
56 lines
1.3 KiB
Zig
const std = @import("../../std.zig");
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const bits = switch (@import("builtin").cpu.arch) {
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.mips,
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.mipsel,
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.mips64,
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.mips64el,
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.powerpc,
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.powerpcle,
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.powerpc64,
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.powerpc64le,
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.sparc,
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.sparc64,
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=> .{ .size = 13, .dir = 3, .none = 1, .read = 2, .write = 4 },
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else => .{ .size = 14, .dir = 2, .none = 0, .read = 2, .write = 1 },
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};
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const Direction = std.meta.Int(.unsigned, bits.dir);
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pub const Request = packed struct {
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nr: u8,
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io_type: u8,
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size: std.meta.Int(.unsigned, bits.size),
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dir: Direction,
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};
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fn io_impl(dir: Direction, io_type: u8, nr: u8, comptime T: type) u32 {
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const request = Request{
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.dir = dir,
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.size = @sizeOf(T),
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.io_type = io_type,
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.nr = nr,
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};
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return @as(u32, @bitCast(request));
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}
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pub fn IO(io_type: u8, nr: u8) u32 {
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return io_impl(bits.none, io_type, nr, void);
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}
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pub fn IOR(io_type: u8, nr: u8, comptime T: type) u32 {
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return io_impl(bits.read, io_type, nr, T);
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}
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pub fn IOW(io_type: u8, nr: u8, comptime T: type) u32 {
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return io_impl(bits.write, io_type, nr, T);
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}
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pub fn IOWR(io_type: u8, nr: u8, comptime T: type) u32 {
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return io_impl(bits.read | bits.write, io_type, nr, T);
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}
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comptime {
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std.debug.assert(@bitSizeOf(Request) == 32);
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}
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