Andrew Kelley 28a9da8bfc stage2: implement while loops (bool condition)
* introduce a dump() function on Module.Fn which helpfully prints to
   stderr the ZIR representation of a function (can be called before
   attempting to codegen it). This is a debugging tool.
 * implement x86 codegen for loops
 * liveness: fix analysis of conditional branches. The logic was buggy
   in a couple ways:
   - it never actually saved the results into the IR instruction (fixed now)
   - it incorrectly labeled operands as dying when their true death was
     after the conditional branch ended (fixed now)
 * zir rendering is enhanced to show liveness analysis results. this
   helps when debugging liveness analysis.
 * fix bug in zir rendering not numbering instructions correctly

closes #6021
2020-08-13 20:32:32 -07:00
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