mirror of
https://github.com/ziglang/zig.git
synced 2025-12-16 11:13:08 +00:00
c2beaba85a
Previously, the registers included r0, r1, r2, r3 which are not included in the callee saved registers according to the Procedure Call Standard for the ARM Architecture.
1271 lines
38 KiB
Zig
1271 lines
38 KiB
Zig
const std = @import("std");
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const DW = std.dwarf;
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const testing = std.testing;
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/// The condition field specifies the flags neccessary for an
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/// Instruction to be executed
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pub const Condition = enum(u4) {
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/// equal
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eq,
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/// not equal
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ne,
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/// unsigned higher or same
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cs,
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/// unsigned lower
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cc,
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/// negative
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mi,
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/// positive or zero
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pl,
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/// overflow
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vs,
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/// no overflow
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vc,
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/// unsigned higer
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hi,
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/// unsigned lower or same
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ls,
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/// greater or equal
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ge,
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/// less than
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lt,
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/// greater than
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gt,
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/// less than or equal
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le,
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/// always
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al,
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/// Converts a std.math.CompareOperator into a condition flag,
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/// i.e. returns the condition that is true iff the result of the
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/// comparison is true. Assumes signed comparison
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pub fn fromCompareOperatorSigned(op: std.math.CompareOperator) Condition {
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return switch (op) {
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.gte => .ge,
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.gt => .gt,
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.neq => .ne,
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.lt => .lt,
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.lte => .le,
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.eq => .eq,
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};
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}
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/// Converts a std.math.CompareOperator into a condition flag,
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/// i.e. returns the condition that is true iff the result of the
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/// comparison is true. Assumes unsigned comparison
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pub fn fromCompareOperatorUnsigned(op: std.math.CompareOperator) Condition {
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return switch (op) {
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.gte => .cs,
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.gt => .hi,
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.neq => .ne,
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.lt => .cc,
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.lte => .ls,
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.eq => .eq,
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};
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}
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/// Returns the condition which is true iff the given condition is
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/// false (if such a condition exists)
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pub fn negate(cond: Condition) Condition {
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return switch (cond) {
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.eq => .ne,
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.ne => .eq,
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.cs => .cc,
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.cc => .cs,
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.mi => .pl,
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.pl => .mi,
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.vs => .vc,
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.vc => .vs,
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.hi => .ls,
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.ls => .hi,
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.ge => .lt,
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.lt => .ge,
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.gt => .le,
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.le => .gt,
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.al => unreachable,
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};
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}
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};
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test "condition from CompareOperator" {
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testing.expectEqual(@as(Condition, .eq), Condition.fromCompareOperatorSigned(.eq));
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testing.expectEqual(@as(Condition, .eq), Condition.fromCompareOperatorUnsigned(.eq));
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testing.expectEqual(@as(Condition, .gt), Condition.fromCompareOperatorSigned(.gt));
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testing.expectEqual(@as(Condition, .hi), Condition.fromCompareOperatorUnsigned(.gt));
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testing.expectEqual(@as(Condition, .le), Condition.fromCompareOperatorSigned(.lte));
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testing.expectEqual(@as(Condition, .ls), Condition.fromCompareOperatorUnsigned(.lte));
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}
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test "negate condition" {
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testing.expectEqual(@as(Condition, .eq), Condition.ne.negate());
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testing.expectEqual(@as(Condition, .ne), Condition.eq.negate());
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}
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/// Represents a register in the ARM instruction set architecture
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pub const Register = enum(u5) {
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r0,
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r1,
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r2,
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r3,
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r4,
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r5,
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r6,
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r7,
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r8,
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r9,
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r10,
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r11,
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r12,
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r13,
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r14,
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r15,
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/// Argument / result / scratch register 1
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a1,
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/// Argument / result / scratch register 2
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a2,
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/// Argument / scratch register 3
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a3,
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/// Argument / scratch register 4
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a4,
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/// Variable-register 1
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v1,
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/// Variable-register 2
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v2,
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/// Variable-register 3
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v3,
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/// Variable-register 4
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v4,
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/// Variable-register 5
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v5,
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/// Platform register
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v6,
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/// Variable-register 7
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v7,
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/// Frame pointer or Variable-register 8
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fp,
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/// Intra-Procedure-call scratch register
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ip,
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/// Stack pointer
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sp,
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/// Link register
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lr,
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/// Program counter
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pc,
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/// Returns the unique 4-bit ID of this register which is used in
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/// the machine code
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pub fn id(self: Register) u4 {
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return @truncate(u4, @enumToInt(self));
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}
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/// Returns the index into `callee_preserved_regs`.
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pub fn allocIndex(self: Register) ?u4 {
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inline for (callee_preserved_regs) |cpreg, i| {
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if (self.id() == cpreg.id()) return i;
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}
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return null;
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}
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pub fn dwarfLocOp(self: Register) u8 {
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return @as(u8, self.id()) + DW.OP_reg0;
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}
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};
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test "Register.id" {
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testing.expectEqual(@as(u4, 15), Register.r15.id());
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testing.expectEqual(@as(u4, 15), Register.pc.id());
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}
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/// Program status registers containing flags, mode bits and other
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/// vital information
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pub const Psr = enum {
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cpsr,
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spsr,
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};
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pub const callee_preserved_regs = [_]Register{ .r4, .r5, .r6, .r7, .r8, .r10 };
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pub const c_abi_int_param_regs = [_]Register{ .r0, .r1, .r2, .r3 };
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pub const c_abi_int_return_regs = [_]Register{ .r0, .r1 };
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/// Represents an instruction in the ARM instruction set architecture
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pub const Instruction = union(enum) {
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DataProcessing: packed struct {
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// Note to self: The order of the fields top-to-bottom is
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// right-to-left in the actual 32-bit int representation
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op2: u12,
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rd: u4,
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rn: u4,
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s: u1,
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opcode: u4,
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i: u1,
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fixed: u2 = 0b00,
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cond: u4,
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},
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Multiply: packed struct {
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rn: u4,
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fixed_1: u4 = 0b1001,
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rm: u4,
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ra: u4,
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rd: u4,
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set_cond: u1,
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accumulate: u1,
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fixed_2: u6 = 0b000000,
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cond: u4,
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},
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MultiplyLong: packed struct {
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rn: u4,
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fixed_1: u4 = 0b1001,
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rm: u4,
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rdlo: u4,
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rdhi: u4,
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set_cond: u1,
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accumulate: u1,
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unsigned: u1,
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fixed_2: u5 = 0b00001,
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cond: u4,
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},
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SingleDataTransfer: packed struct {
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offset: u12,
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rd: u4,
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rn: u4,
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load_store: u1,
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write_back: u1,
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byte_word: u1,
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up_down: u1,
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pre_post: u1,
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imm: u1,
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fixed: u2 = 0b01,
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cond: u4,
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},
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ExtraLoadStore: packed struct {
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imm4l: u4,
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fixed_1: u1 = 0b1,
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op2: u2,
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fixed_2: u1 = 0b1,
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imm4h: u4,
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rt: u4,
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rn: u4,
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o1: u1,
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write_back: u1,
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imm: u1,
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up_down: u1,
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pre_index: u1,
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fixed_3: u3 = 0b000,
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cond: u4,
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},
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BlockDataTransfer: packed struct {
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register_list: u16,
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rn: u4,
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load_store: u1,
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write_back: u1,
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psr_or_user: u1,
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up_down: u1,
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pre_post: u1,
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fixed: u3 = 0b100,
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cond: u4,
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},
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Branch: packed struct {
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offset: u24,
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link: u1,
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fixed: u3 = 0b101,
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cond: u4,
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},
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BranchExchange: packed struct {
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rn: u4,
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fixed_1: u1 = 0b1,
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link: u1,
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fixed_2: u22 = 0b0001_0010_1111_1111_1111_00,
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cond: u4,
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},
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SupervisorCall: packed struct {
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comment: u24,
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fixed: u4 = 0b1111,
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cond: u4,
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},
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Breakpoint: packed struct {
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imm4: u4,
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fixed_1: u4 = 0b0111,
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imm12: u12,
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fixed_2_and_cond: u12 = 0b1110_0001_0010,
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},
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/// Represents the possible operations which can be performed by a
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/// DataProcessing instruction
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const Opcode = enum(u4) {
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// Rd := Op1 AND Op2
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@"and",
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// Rd := Op1 EOR Op2
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eor,
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// Rd := Op1 - Op2
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sub,
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// Rd := Op2 - Op1
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rsb,
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// Rd := Op1 + Op2
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add,
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// Rd := Op1 + Op2 + C
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adc,
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// Rd := Op1 - Op2 + C - 1
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sbc,
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// Rd := Op2 - Op1 + C - 1
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rsc,
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// set condition codes on Op1 AND Op2
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tst,
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// set condition codes on Op1 EOR Op2
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teq,
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// set condition codes on Op1 - Op2
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cmp,
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// set condition codes on Op1 + Op2
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cmn,
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// Rd := Op1 OR Op2
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orr,
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// Rd := Op2
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mov,
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// Rd := Op1 AND NOT Op2
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bic,
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// Rd := NOT Op2
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mvn,
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};
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/// Represents the second operand to a data processing instruction
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/// which can either be content from a register or an immediate
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/// value
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pub const Operand = union(enum) {
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Register: packed struct {
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rm: u4,
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shift: u8,
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},
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Immediate: packed struct {
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imm: u8,
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rotate: u4,
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},
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/// Represents multiple ways a register can be shifted. A
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/// register can be shifted by a specific immediate value or
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/// by the contents of another register
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pub const Shift = union(enum) {
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Immediate: packed struct {
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fixed: u1 = 0b0,
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typ: u2,
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amount: u5,
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},
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Register: packed struct {
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fixed_1: u1 = 0b1,
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typ: u2,
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fixed_2: u1 = 0b0,
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rs: u4,
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},
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pub const Type = enum(u2) {
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logical_left,
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logical_right,
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arithmetic_right,
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rotate_right,
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};
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pub const none = Shift{
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.Immediate = .{
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.amount = 0,
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.typ = 0,
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},
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};
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pub fn toU8(self: Shift) u8 {
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return switch (self) {
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.Register => |v| @bitCast(u8, v),
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.Immediate => |v| @bitCast(u8, v),
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};
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}
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pub fn reg(rs: Register, typ: Type) Shift {
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return Shift{
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.Register = .{
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.rs = rs.id(),
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.typ = @enumToInt(typ),
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},
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};
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}
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pub fn imm(amount: u5, typ: Type) Shift {
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return Shift{
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.Immediate = .{
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.amount = amount,
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.typ = @enumToInt(typ),
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},
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};
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}
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};
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pub fn toU12(self: Operand) u12 {
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return switch (self) {
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.Register => |v| @bitCast(u12, v),
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.Immediate => |v| @bitCast(u12, v),
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};
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}
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pub fn reg(rm: Register, shift: Shift) Operand {
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return Operand{
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.Register = .{
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.rm = rm.id(),
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.shift = shift.toU8(),
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},
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};
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}
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pub fn imm(immediate: u8, rotate: u4) Operand {
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return Operand{
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.Immediate = .{
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.imm = immediate,
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.rotate = rotate,
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},
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};
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}
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/// Tries to convert an unsigned 32 bit integer into an
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/// immediate operand using rotation. Returns null when there
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/// is no conversion
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pub fn fromU32(x: u32) ?Operand {
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const masks = comptime blk: {
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const base_mask: u32 = std.math.maxInt(u8);
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var result = [_]u32{0} ** 16;
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for (result) |*mask, i| mask.* = std.math.rotr(u32, base_mask, 2 * i);
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break :blk result;
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};
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return for (masks) |mask, i| {
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if (x & mask == x) {
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break Operand{
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.Immediate = .{
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.imm = @intCast(u8, std.math.rotl(u32, x, 2 * i)),
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.rotate = @intCast(u4, i),
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},
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};
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}
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} else null;
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}
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};
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/// Represents the offset operand of a load or store
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/// instruction. Data can be loaded from memory with either an
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/// immediate offset or an offset that is stored in some register.
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pub const Offset = union(enum) {
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Immediate: u12,
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Register: packed struct {
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rm: u4,
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shift: u8,
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},
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pub const none = Offset{
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.Immediate = 0,
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};
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pub fn toU12(self: Offset) u12 {
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return switch (self) {
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.Register => |v| @bitCast(u12, v),
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.Immediate => |v| v,
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};
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}
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pub fn reg(rm: Register, shift: u8) Offset {
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return Offset{
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.Register = .{
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.rm = rm.id(),
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.shift = shift,
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},
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};
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}
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pub fn imm(immediate: u12) Offset {
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return Offset{
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.Immediate = immediate,
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};
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}
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};
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/// Represents the offset operand of an extra load or store
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/// instruction.
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pub const ExtraLoadStoreOffset = union(enum) {
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immediate: u8,
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register: u4,
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pub const none = ExtraLoadStoreOffset{
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.immediate = 0,
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};
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pub fn reg(register: Register) ExtraLoadStoreOffset {
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return ExtraLoadStoreOffset{
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.register = register.id(),
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};
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}
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pub fn imm(immediate: u8) ExtraLoadStoreOffset {
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return ExtraLoadStoreOffset{
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.immediate = immediate,
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};
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}
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};
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/// Represents the register list operand to a block data transfer
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/// instruction
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pub const RegisterList = packed struct {
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r0: bool = false,
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r1: bool = false,
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r2: bool = false,
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r3: bool = false,
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r4: bool = false,
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r5: bool = false,
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r6: bool = false,
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r7: bool = false,
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r8: bool = false,
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r9: bool = false,
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r10: bool = false,
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r11: bool = false,
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r12: bool = false,
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r13: bool = false,
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r14: bool = false,
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r15: bool = false,
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};
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pub fn toU32(self: Instruction) u32 {
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return switch (self) {
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.DataProcessing => |v| @bitCast(u32, v),
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.Multiply => |v| @bitCast(u32, v),
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.MultiplyLong => |v| @bitCast(u32, v),
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.SingleDataTransfer => |v| @bitCast(u32, v),
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.ExtraLoadStore => |v| @bitCast(u32, v),
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.BlockDataTransfer => |v| @bitCast(u32, v),
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.Branch => |v| @bitCast(u32, v),
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.BranchExchange => |v| @bitCast(u32, v),
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.SupervisorCall => |v| @bitCast(u32, v),
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.Breakpoint => |v| @intCast(u32, v.imm4) | (@intCast(u32, v.fixed_1) << 4) | (@intCast(u32, v.imm12) << 8) | (@intCast(u32, v.fixed_2_and_cond) << 20),
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};
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}
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|
|
// Helper functions for the "real" functions below
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|
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fn dataProcessing(
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cond: Condition,
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opcode: Opcode,
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s: u1,
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rd: Register,
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rn: Register,
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op2: Operand,
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) Instruction {
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return Instruction{
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.DataProcessing = .{
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.cond = @enumToInt(cond),
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.i = @boolToInt(op2 == .Immediate),
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.opcode = @enumToInt(opcode),
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.s = s,
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.rn = rn.id(),
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.rd = rd.id(),
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.op2 = op2.toU12(),
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},
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};
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}
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|
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fn specialMov(
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cond: Condition,
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rd: Register,
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imm: u16,
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top: bool,
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|
) Instruction {
|
|
return Instruction{
|
|
.DataProcessing = .{
|
|
.cond = @enumToInt(cond),
|
|
.i = 1,
|
|
.opcode = if (top) 0b1010 else 0b1000,
|
|
.s = 0,
|
|
.rn = @truncate(u4, imm >> 12),
|
|
.rd = rd.id(),
|
|
.op2 = @truncate(u12, imm),
|
|
},
|
|
};
|
|
}
|
|
|
|
fn multiply(
|
|
cond: Condition,
|
|
set_cond: u1,
|
|
rd: Register,
|
|
rn: Register,
|
|
rm: Register,
|
|
ra: ?Register,
|
|
) Instruction {
|
|
return Instruction{
|
|
.Multiply = .{
|
|
.cond = @enumToInt(cond),
|
|
.accumulate = @boolToInt(ra != null),
|
|
.set_cond = set_cond,
|
|
.rd = rd.id(),
|
|
.rn = rn.id(),
|
|
.ra = if (ra) |reg| reg.id() else 0b0000,
|
|
.rm = rm.id(),
|
|
},
|
|
};
|
|
}
|
|
|
|
fn multiplyLong(
|
|
cond: Condition,
|
|
signed: u1,
|
|
accumulate: u1,
|
|
set_cond: u1,
|
|
rdhi: Register,
|
|
rdlo: Register,
|
|
rm: Register,
|
|
rn: Register,
|
|
) Instruction {
|
|
return Instruction{
|
|
.MultiplyLong = .{
|
|
.cond = @enumToInt(cond),
|
|
.unsigned = signed,
|
|
.accumulate = accumulate,
|
|
.set_cond = set_cond,
|
|
.rdlo = rdlo.id(),
|
|
.rdhi = rdhi.id(),
|
|
.rn = rn.id(),
|
|
.rm = rm.id(),
|
|
},
|
|
};
|
|
}
|
|
|
|
fn singleDataTransfer(
|
|
cond: Condition,
|
|
rd: Register,
|
|
rn: Register,
|
|
offset: Offset,
|
|
pre_index: bool,
|
|
positive: bool,
|
|
byte_word: u1,
|
|
write_back: bool,
|
|
load_store: u1,
|
|
) Instruction {
|
|
return Instruction{
|
|
.SingleDataTransfer = .{
|
|
.cond = @enumToInt(cond),
|
|
.rn = rn.id(),
|
|
.rd = rd.id(),
|
|
.offset = offset.toU12(),
|
|
.load_store = load_store,
|
|
.write_back = @boolToInt(write_back),
|
|
.byte_word = byte_word,
|
|
.up_down = @boolToInt(positive),
|
|
.pre_post = @boolToInt(pre_index),
|
|
.imm = @boolToInt(offset != .Immediate),
|
|
},
|
|
};
|
|
}
|
|
|
|
fn extraLoadStore(
|
|
cond: Condition,
|
|
pre_index: bool,
|
|
positive: bool,
|
|
write_back: bool,
|
|
o1: u1,
|
|
op2: u2,
|
|
rn: Register,
|
|
rt: Register,
|
|
offset: ExtraLoadStoreOffset,
|
|
) Instruction {
|
|
const imm4l: u4 = switch (offset) {
|
|
.immediate => |imm| @truncate(u4, imm),
|
|
.register => |reg| reg,
|
|
};
|
|
const imm4h: u4 = switch (offset) {
|
|
.immediate => |imm| @truncate(u4, imm >> 4),
|
|
.register => |reg| 0b0000,
|
|
};
|
|
|
|
return Instruction{
|
|
.ExtraLoadStore = .{
|
|
.imm4l = imm4l,
|
|
.op2 = op2,
|
|
.imm4h = imm4h,
|
|
.rt = rt.id(),
|
|
.rn = rn.id(),
|
|
.o1 = o1,
|
|
.write_back = @boolToInt(write_back),
|
|
.imm = @boolToInt(offset == .immediate),
|
|
.up_down = @boolToInt(positive),
|
|
.pre_index = @boolToInt(pre_index),
|
|
.cond = @enumToInt(cond),
|
|
},
|
|
};
|
|
}
|
|
|
|
fn blockDataTransfer(
|
|
cond: Condition,
|
|
rn: Register,
|
|
reg_list: RegisterList,
|
|
pre_post: u1,
|
|
up_down: u1,
|
|
psr_or_user: u1,
|
|
write_back: bool,
|
|
load_store: u1,
|
|
) Instruction {
|
|
return Instruction{
|
|
.BlockDataTransfer = .{
|
|
.register_list = @bitCast(u16, reg_list),
|
|
.rn = rn.id(),
|
|
.load_store = load_store,
|
|
.write_back = @boolToInt(write_back),
|
|
.psr_or_user = psr_or_user,
|
|
.up_down = up_down,
|
|
.pre_post = pre_post,
|
|
.cond = @enumToInt(cond),
|
|
},
|
|
};
|
|
}
|
|
|
|
fn branch(cond: Condition, offset: i26, link: u1) Instruction {
|
|
return Instruction{
|
|
.Branch = .{
|
|
.cond = @enumToInt(cond),
|
|
.link = link,
|
|
.offset = @bitCast(u24, @intCast(i24, offset >> 2)),
|
|
},
|
|
};
|
|
}
|
|
|
|
fn branchExchange(cond: Condition, rn: Register, link: u1) Instruction {
|
|
return Instruction{
|
|
.BranchExchange = .{
|
|
.cond = @enumToInt(cond),
|
|
.link = link,
|
|
.rn = rn.id(),
|
|
},
|
|
};
|
|
}
|
|
|
|
fn supervisorCall(cond: Condition, comment: u24) Instruction {
|
|
return Instruction{
|
|
.SupervisorCall = .{
|
|
.cond = @enumToInt(cond),
|
|
.comment = comment,
|
|
},
|
|
};
|
|
}
|
|
|
|
fn breakpoint(imm: u16) Instruction {
|
|
return Instruction{
|
|
.Breakpoint = .{
|
|
.imm12 = @truncate(u12, imm >> 4),
|
|
.imm4 = @truncate(u4, imm),
|
|
},
|
|
};
|
|
}
|
|
|
|
// Public functions replicating assembler syntax as closely as
|
|
// possible
|
|
|
|
// Data processing
|
|
|
|
pub fn @"and"(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
|
return dataProcessing(cond, .@"and", 0, rd, rn, op2);
|
|
}
|
|
|
|
pub fn ands(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
|
return dataProcessing(cond, .@"and", 1, rd, rn, op2);
|
|
}
|
|
|
|
pub fn eor(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
|
return dataProcessing(cond, .eor, 0, rd, rn, op2);
|
|
}
|
|
|
|
pub fn eors(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
|
return dataProcessing(cond, .eor, 1, rd, rn, op2);
|
|
}
|
|
|
|
pub fn sub(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
|
return dataProcessing(cond, .sub, 0, rd, rn, op2);
|
|
}
|
|
|
|
pub fn subs(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
|
return dataProcessing(cond, .sub, 1, rd, rn, op2);
|
|
}
|
|
|
|
pub fn rsb(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
|
return dataProcessing(cond, .rsb, 0, rd, rn, op2);
|
|
}
|
|
|
|
pub fn rsbs(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
|
return dataProcessing(cond, .rsb, 1, rd, rn, op2);
|
|
}
|
|
|
|
pub fn add(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
|
return dataProcessing(cond, .add, 0, rd, rn, op2);
|
|
}
|
|
|
|
pub fn adds(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
|
return dataProcessing(cond, .add, 1, rd, rn, op2);
|
|
}
|
|
|
|
pub fn adc(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
|
return dataProcessing(cond, .adc, 0, rd, rn, op2);
|
|
}
|
|
|
|
pub fn adcs(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
|
return dataProcessing(cond, .adc, 1, rd, rn, op2);
|
|
}
|
|
|
|
pub fn sbc(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
|
return dataProcessing(cond, .sbc, 0, rd, rn, op2);
|
|
}
|
|
|
|
pub fn sbcs(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
|
return dataProcessing(cond, .sbc, 1, rd, rn, op2);
|
|
}
|
|
|
|
pub fn rsc(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
|
return dataProcessing(cond, .rsc, 0, rd, rn, op2);
|
|
}
|
|
|
|
pub fn rscs(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
|
return dataProcessing(cond, .rsc, 1, rd, rn, op2);
|
|
}
|
|
|
|
pub fn tst(cond: Condition, rn: Register, op2: Operand) Instruction {
|
|
return dataProcessing(cond, .tst, 1, .r0, rn, op2);
|
|
}
|
|
|
|
pub fn teq(cond: Condition, rn: Register, op2: Operand) Instruction {
|
|
return dataProcessing(cond, .teq, 1, .r0, rn, op2);
|
|
}
|
|
|
|
pub fn cmp(cond: Condition, rn: Register, op2: Operand) Instruction {
|
|
return dataProcessing(cond, .cmp, 1, .r0, rn, op2);
|
|
}
|
|
|
|
pub fn cmn(cond: Condition, rn: Register, op2: Operand) Instruction {
|
|
return dataProcessing(cond, .cmn, 1, .r0, rn, op2);
|
|
}
|
|
|
|
pub fn orr(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
|
return dataProcessing(cond, .orr, 0, rd, rn, op2);
|
|
}
|
|
|
|
pub fn orrs(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
|
return dataProcessing(cond, .orr, 1, rd, rn, op2);
|
|
}
|
|
|
|
pub fn mov(cond: Condition, rd: Register, op2: Operand) Instruction {
|
|
return dataProcessing(cond, .mov, 0, rd, .r0, op2);
|
|
}
|
|
|
|
pub fn movs(cond: Condition, rd: Register, op2: Operand) Instruction {
|
|
return dataProcessing(cond, .mov, 1, rd, .r0, op2);
|
|
}
|
|
|
|
pub fn bic(cond: Condition, rd: Register, op2: Operand) Instruction {
|
|
return dataProcessing(cond, .bic, 0, rd, rn, op2);
|
|
}
|
|
|
|
pub fn bics(cond: Condition, rd: Register, op2: Operand) Instruction {
|
|
return dataProcessing(cond, .bic, 1, rd, rn, op2);
|
|
}
|
|
|
|
pub fn mvn(cond: Condition, rd: Register, op2: Operand) Instruction {
|
|
return dataProcessing(cond, .mvn, 0, rd, .r0, op2);
|
|
}
|
|
|
|
pub fn mvns(cond: Condition, rd: Register, op2: Operand) Instruction {
|
|
return dataProcessing(cond, .mvn, 1, rd, .r0, op2);
|
|
}
|
|
|
|
// movw and movt
|
|
|
|
pub fn movw(cond: Condition, rd: Register, imm: u16) Instruction {
|
|
return specialMov(cond, rd, imm, false);
|
|
}
|
|
|
|
pub fn movt(cond: Condition, rd: Register, imm: u16) Instruction {
|
|
return specialMov(cond, rd, imm, true);
|
|
}
|
|
|
|
// PSR transfer
|
|
|
|
pub fn mrs(cond: Condition, rd: Register, psr: Psr) Instruction {
|
|
return Instruction{
|
|
.DataProcessing = .{
|
|
.cond = @enumToInt(cond),
|
|
.i = 0,
|
|
.opcode = if (psr == .spsr) 0b1010 else 0b1000,
|
|
.s = 0,
|
|
.rn = 0b1111,
|
|
.rd = rd.id(),
|
|
.op2 = 0b0000_0000_0000,
|
|
},
|
|
};
|
|
}
|
|
|
|
pub fn msr(cond: Condition, psr: Psr, op: Operand) Instruction {
|
|
return Instruction{
|
|
.DataProcessing = .{
|
|
.cond = @enumToInt(cond),
|
|
.i = 0,
|
|
.opcode = if (psr == .spsr) 0b1011 else 0b1001,
|
|
.s = 0,
|
|
.rn = 0b1111,
|
|
.rd = 0b1111,
|
|
.op2 = op.toU12(),
|
|
},
|
|
};
|
|
}
|
|
|
|
// Multiply
|
|
|
|
pub fn mul(cond: Condition, rd: Register, rn: Register, rm: Register) Instruction {
|
|
return multiply(cond, 0, rd, rn, rm, null);
|
|
}
|
|
|
|
pub fn muls(cond: Condition, rd: Register, rn: Register, rm: Register) Instruction {
|
|
return multiply(cond, 1, rd, rn, rm, null);
|
|
}
|
|
|
|
pub fn mla(cond: Condition, rd: Register, rn: Register, rm: Register, ra: Register) Instruction {
|
|
return multiply(cond, 0, rd, rn, rm, ra);
|
|
}
|
|
|
|
pub fn mlas(cond: Condition, rd: Register, rn: Register, rm: Register, ra: Register) Instruction {
|
|
return multiply(cond, 1, rd, rn, rm, ra);
|
|
}
|
|
|
|
// Multiply long
|
|
|
|
pub fn umull(cond: Condition, rdlo: Register, rdhi: Register, rn: Register, rm: Register) Instruction {
|
|
return multiplyLong(cond, 0, 0, 0, rdhi, rdlo, rm, rn);
|
|
}
|
|
|
|
pub fn umulls(cond: Condition, rdlo: Register, rdhi: Register, rn: Register, rm: Register) Instruction {
|
|
return multiplyLong(cond, 0, 0, 1, rdhi, rdlo, rm, rn);
|
|
}
|
|
|
|
pub fn umlal(cond: Condition, rdlo: Register, rdhi: Register, rn: Register, rm: Register) Instruction {
|
|
return multiplyLong(cond, 0, 1, 0, rdhi, rdlo, rm, rn);
|
|
}
|
|
|
|
pub fn umlals(cond: Condition, rdlo: Register, rdhi: Register, rn: Register, rm: Register) Instruction {
|
|
return multiplyLong(cond, 0, 1, 1, rdhi, rdlo, rm, rn);
|
|
}
|
|
|
|
pub fn smull(cond: Condition, rdlo: Register, rdhi: Register, rn: Register, rm: Register) Instruction {
|
|
return multiplyLong(cond, 1, 0, 0, rdhi, rdlo, rm, rn);
|
|
}
|
|
|
|
pub fn smulls(cond: Condition, rdlo: Register, rdhi: Register, rn: Register, rm: Register) Instruction {
|
|
return multiplyLong(cond, 1, 0, 1, rdhi, rdlo, rm, rn);
|
|
}
|
|
|
|
pub fn smlal(cond: Condition, rdlo: Register, rdhi: Register, rn: Register, rm: Register) Instruction {
|
|
return multiplyLong(cond, 1, 1, 0, rdhi, rdlo, rm, rn);
|
|
}
|
|
|
|
pub fn smlals(cond: Condition, rdlo: Register, rdhi: Register, rn: Register, rm: Register) Instruction {
|
|
return multiplyLong(cond, 1, 1, 1, rdhi, rdlo, rm, rn);
|
|
}
|
|
|
|
// Single data transfer
|
|
|
|
pub const OffsetArgs = struct {
|
|
pre_index: bool = true,
|
|
positive: bool = true,
|
|
offset: Offset,
|
|
write_back: bool = false,
|
|
};
|
|
|
|
pub fn ldr(cond: Condition, rd: Register, rn: Register, args: OffsetArgs) Instruction {
|
|
return singleDataTransfer(cond, rd, rn, args.offset, args.pre_index, args.positive, 0, args.write_back, 1);
|
|
}
|
|
|
|
pub fn ldrb(cond: Condition, rd: Register, rn: Register, args: OffsetArgs) Instruction {
|
|
return singleDataTransfer(cond, rd, rn, args.offset, args.pre_index, args.positive, 1, args.write_back, 1);
|
|
}
|
|
|
|
pub fn str(cond: Condition, rd: Register, rn: Register, args: OffsetArgs) Instruction {
|
|
return singleDataTransfer(cond, rd, rn, args.offset, args.pre_index, args.positive, 0, args.write_back, 0);
|
|
}
|
|
|
|
pub fn strb(cond: Condition, rd: Register, rn: Register, args: OffsetArgs) Instruction {
|
|
return singleDataTransfer(cond, rd, rn, args.offset, args.pre_index, args.positive, 1, args.write_back, 0);
|
|
}
|
|
|
|
// Extra load/store
|
|
|
|
pub const ExtraLoadStoreOffsetArgs = struct {
|
|
pre_index: bool = true,
|
|
positive: bool = true,
|
|
offset: ExtraLoadStoreOffset,
|
|
write_back: bool = false,
|
|
};
|
|
|
|
pub fn strh(cond: Condition, rt: Register, rn: Register, args: ExtraLoadStoreOffsetArgs) Instruction {
|
|
return extraLoadStore(cond, args.pre_index, args.positive, args.write_back, 0, 0b01, rn, rt, args.offset);
|
|
}
|
|
|
|
pub fn ldrh(cond: Condition, rt: Register, rn: Register, args: ExtraLoadStoreOffsetArgs) Instruction {
|
|
return extraLoadStore(cond, args.pre_index, args.positive, args.write_back, 1, 0b01, rn, rt, args.offset);
|
|
}
|
|
|
|
// Block data transfer
|
|
|
|
pub fn ldmda(cond: Condition, rn: Register, write_back: bool, reg_list: RegisterList) Instruction {
|
|
return blockDataTransfer(cond, rn, reg_list, 0, 0, 0, write_back, 1);
|
|
}
|
|
|
|
pub fn ldmdb(cond: Condition, rn: Register, write_back: bool, reg_list: RegisterList) Instruction {
|
|
return blockDataTransfer(cond, rn, reg_list, 1, 0, 0, write_back, 1);
|
|
}
|
|
|
|
pub fn ldmib(cond: Condition, rn: Register, write_back: bool, reg_list: RegisterList) Instruction {
|
|
return blockDataTransfer(cond, rn, reg_list, 1, 1, 0, write_back, 1);
|
|
}
|
|
|
|
pub fn ldmia(cond: Condition, rn: Register, write_back: bool, reg_list: RegisterList) Instruction {
|
|
return blockDataTransfer(cond, rn, reg_list, 0, 1, 0, write_back, 1);
|
|
}
|
|
|
|
pub const ldmfa = ldmda;
|
|
pub const ldmea = ldmdb;
|
|
pub const ldmed = ldmib;
|
|
pub const ldmfd = ldmia;
|
|
pub const ldm = ldmia;
|
|
|
|
pub fn stmda(cond: Condition, rn: Register, write_back: bool, reg_list: RegisterList) Instruction {
|
|
return blockDataTransfer(cond, rn, reg_list, 0, 0, 0, write_back, 0);
|
|
}
|
|
|
|
pub fn stmdb(cond: Condition, rn: Register, write_back: bool, reg_list: RegisterList) Instruction {
|
|
return blockDataTransfer(cond, rn, reg_list, 1, 0, 0, write_back, 0);
|
|
}
|
|
|
|
pub fn stmib(cond: Condition, rn: Register, write_back: bool, reg_list: RegisterList) Instruction {
|
|
return blockDataTransfer(cond, rn, reg_list, 1, 1, 0, write_back, 0);
|
|
}
|
|
|
|
pub fn stmia(cond: Condition, rn: Register, write_back: bool, reg_list: RegisterList) Instruction {
|
|
return blockDataTransfer(cond, rn, reg_list, 0, 1, 0, write_back, 0);
|
|
}
|
|
|
|
pub const stmed = stmda;
|
|
pub const stmfd = stmdb;
|
|
pub const stmfa = stmib;
|
|
pub const stmea = stmia;
|
|
pub const stm = stmia;
|
|
|
|
// Branch
|
|
|
|
pub fn b(cond: Condition, offset: i26) Instruction {
|
|
return branch(cond, offset, 0);
|
|
}
|
|
|
|
pub fn bl(cond: Condition, offset: i26) Instruction {
|
|
return branch(cond, offset, 1);
|
|
}
|
|
|
|
// Branch and exchange
|
|
|
|
pub fn bx(cond: Condition, rn: Register) Instruction {
|
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return branchExchange(cond, rn, 0);
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}
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pub fn blx(cond: Condition, rn: Register) Instruction {
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return branchExchange(cond, rn, 1);
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}
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// Supervisor Call
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pub const swi = svc;
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|
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pub fn svc(cond: Condition, comment: u24) Instruction {
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return supervisorCall(cond, comment);
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}
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|
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// Breakpoint
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|
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pub fn bkpt(imm: u16) Instruction {
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return breakpoint(imm);
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}
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// Aliases
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pub fn nop() Instruction {
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return mov(.al, .r0, Instruction.Operand.reg(.r0, Instruction.Operand.Shift.none));
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}
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pub fn pop(cond: Condition, args: anytype) Instruction {
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if (@typeInfo(@TypeOf(args)) != .Struct) {
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@compileError("Expected tuple or struct argument, found " ++ @typeName(@TypeOf(args)));
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|
}
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|
|
|
if (args.len < 1) {
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@compileError("Expected at least one register");
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|
} else if (args.len == 1) {
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const reg = args[0];
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|
return ldr(cond, reg, .sp, .{
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.pre_index = false,
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.positive = true,
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.offset = Offset.imm(4),
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|
.write_back = false,
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|
});
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|
} else {
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var register_list: u16 = 0;
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inline for (args) |arg| {
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const reg = @as(Register, arg);
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register_list |= @as(u16, 1) << reg.id();
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}
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|
return ldm(cond, .sp, true, @bitCast(RegisterList, register_list));
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|
}
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|
}
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|
|
|
pub fn push(cond: Condition, args: anytype) Instruction {
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|
if (@typeInfo(@TypeOf(args)) != .Struct) {
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|
@compileError("Expected tuple or struct argument, found " ++ @typeName(@TypeOf(args)));
|
|
}
|
|
|
|
if (args.len < 1) {
|
|
@compileError("Expected at least one register");
|
|
} else if (args.len == 1) {
|
|
const reg = args[0];
|
|
return str(cond, reg, .sp, .{
|
|
.pre_index = true,
|
|
.positive = false,
|
|
.offset = Offset.imm(4),
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|
.write_back = true,
|
|
});
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|
} else {
|
|
var register_list: u16 = 0;
|
|
inline for (args) |arg| {
|
|
const reg = @as(Register, arg);
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|
register_list |= @as(u16, 1) << reg.id();
|
|
}
|
|
return stmdb(cond, .sp, true, @bitCast(RegisterList, register_list));
|
|
}
|
|
}
|
|
};
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|
|
|
test "serialize instructions" {
|
|
const Testcase = struct {
|
|
inst: Instruction,
|
|
expected: u32,
|
|
};
|
|
|
|
const testcases = [_]Testcase{
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|
.{ // add r0, r0, r0
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|
.inst = Instruction.add(.al, .r0, .r0, Instruction.Operand.reg(.r0, Instruction.Operand.Shift.none)),
|
|
.expected = 0b1110_00_0_0100_0_0000_0000_00000000_0000,
|
|
},
|
|
.{ // mov r4, r2
|
|
.inst = Instruction.mov(.al, .r4, Instruction.Operand.reg(.r2, Instruction.Operand.Shift.none)),
|
|
.expected = 0b1110_00_0_1101_0_0000_0100_00000000_0010,
|
|
},
|
|
.{ // mov r0, #42
|
|
.inst = Instruction.mov(.al, .r0, Instruction.Operand.imm(42, 0)),
|
|
.expected = 0b1110_00_1_1101_0_0000_0000_0000_00101010,
|
|
},
|
|
.{ // mrs r5, cpsr
|
|
.inst = Instruction.mrs(.al, .r5, .cpsr),
|
|
.expected = 0b1110_00010_0_001111_0101_000000000000,
|
|
},
|
|
.{ // mul r0, r1, r2
|
|
.inst = Instruction.mul(.al, .r0, .r1, .r2),
|
|
.expected = 0b1110_000000_0_0_0000_0000_0010_1001_0001,
|
|
},
|
|
.{ // umlal r0, r1, r5, r6
|
|
.inst = Instruction.umlal(.al, .r0, .r1, .r5, .r6),
|
|
.expected = 0b1110_00001_0_1_0_0001_0000_0110_1001_0101,
|
|
},
|
|
.{ // ldr r0, [r2, #42]
|
|
.inst = Instruction.ldr(.al, .r0, .r2, .{
|
|
.offset = Instruction.Offset.imm(42),
|
|
}),
|
|
.expected = 0b1110_01_0_1_1_0_0_1_0010_0000_000000101010,
|
|
},
|
|
.{ // str r0, [r3]
|
|
.inst = Instruction.str(.al, .r0, .r3, .{
|
|
.offset = Instruction.Offset.none,
|
|
}),
|
|
.expected = 0b1110_01_0_1_1_0_0_0_0011_0000_000000000000,
|
|
},
|
|
.{ // strh r1, [r5]
|
|
.inst = Instruction.strh(.al, .r1, .r5, .{
|
|
.offset = Instruction.ExtraLoadStoreOffset.none,
|
|
}),
|
|
.expected = 0b1110_000_1_1_1_0_0_0101_0001_0000_1011_0000,
|
|
},
|
|
.{ // b #12
|
|
.inst = Instruction.b(.al, 12),
|
|
.expected = 0b1110_101_0_0000_0000_0000_0000_0000_0011,
|
|
},
|
|
.{ // bl #-4
|
|
.inst = Instruction.bl(.al, -4),
|
|
.expected = 0b1110_101_1_1111_1111_1111_1111_1111_1111,
|
|
},
|
|
.{ // bx lr
|
|
.inst = Instruction.bx(.al, .lr),
|
|
.expected = 0b1110_0001_0010_1111_1111_1111_0001_1110,
|
|
},
|
|
.{ // svc #0
|
|
.inst = Instruction.svc(.al, 0),
|
|
.expected = 0b1110_1111_0000_0000_0000_0000_0000_0000,
|
|
},
|
|
.{ // bkpt #42
|
|
.inst = Instruction.bkpt(42),
|
|
.expected = 0b1110_0001_0010_000000000010_0111_1010,
|
|
},
|
|
.{ // stmdb r9, {r0}
|
|
.inst = Instruction.stmdb(.al, .r9, false, .{ .r0 = true }),
|
|
.expected = 0b1110_100_1_0_0_0_0_1001_0000000000000001,
|
|
},
|
|
.{ // ldmea r4!, {r2, r5}
|
|
.inst = Instruction.ldmea(.al, .r4, true, .{ .r2 = true, .r5 = true }),
|
|
.expected = 0b1110_100_1_0_0_1_1_0100_0000000000100100,
|
|
},
|
|
};
|
|
|
|
for (testcases) |case| {
|
|
const actual = case.inst.toU32();
|
|
testing.expectEqual(case.expected, actual);
|
|
}
|
|
}
|
|
|
|
test "aliases" {
|
|
const Testcase = struct {
|
|
expected: Instruction,
|
|
actual: Instruction,
|
|
};
|
|
|
|
const testcases = [_]Testcase{
|
|
.{ // pop { r6 }
|
|
.actual = Instruction.pop(.al, .{.r6}),
|
|
.expected = Instruction.ldr(.al, .r6, .sp, .{
|
|
.pre_index = false,
|
|
.positive = true,
|
|
.offset = Instruction.Offset.imm(4),
|
|
.write_back = false,
|
|
}),
|
|
},
|
|
.{ // pop { r1, r5 }
|
|
.actual = Instruction.pop(.al, .{ .r1, .r5 }),
|
|
.expected = Instruction.ldm(.al, .sp, true, .{ .r1 = true, .r5 = true }),
|
|
},
|
|
.{ // push { r3 }
|
|
.actual = Instruction.push(.al, .{.r3}),
|
|
.expected = Instruction.str(.al, .r3, .sp, .{
|
|
.pre_index = true,
|
|
.positive = false,
|
|
.offset = Instruction.Offset.imm(4),
|
|
.write_back = true,
|
|
}),
|
|
},
|
|
.{ // push { r0, r2 }
|
|
.actual = Instruction.push(.al, .{ .r0, .r2 }),
|
|
.expected = Instruction.stmdb(.al, .sp, true, .{ .r0 = true, .r2 = true }),
|
|
},
|
|
};
|
|
|
|
for (testcases) |case| {
|
|
testing.expectEqual(case.expected.toU32(), case.actual.toU32());
|
|
}
|
|
}
|