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553cb3ed46
sys/param.h was manually adjusted to not define __NetBSD_Version__ since it will be defined by the compiler.
337 lines
11 KiB
C
Vendored
337 lines
11 KiB
C
Vendored
/* $NetBSD: sysreg.h,v 1.28 2022/12/03 11:09:59 skrll Exp $ */
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/*
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* Copyright (c) 2014 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas of 3am Software Foundry.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _RISCV_SYSREG_H_
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#define _RISCV_SYSREG_H_
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#ifndef _KERNEL
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#include <sys/param.h>
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#endif
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#include <riscv/reg.h>
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#define FCSR_FMASK 0 // no exception bits
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#define FCSR_FRM __BITS(7, 5)
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#define FCSR_FRM_RNE 0b000 // Round Nearest, ties to Even
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#define FCSR_FRM_RTZ 0b001 // Round Towards Zero
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#define FCSR_FRM_RDN 0b010 // Round DowN (-infinity)
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#define FCSR_FRM_RUP 0b011 // Round UP (+infinity)
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#define FCSR_FRM_RMM 0b100 // Round to nearest, ties to Max Magnitude
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#define FCSR_FRM_DYN 0b111 // Dynamic rounding
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#define FCSR_FFLAGS __BITS(4, 0) // Sticky bits
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#define FCSR_NV __BIT(4) // iNValid operation
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#define FCSR_DZ __BIT(3) // Divide by Zero
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#define FCSR_OF __BIT(2) // OverFlow
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#define FCSR_UF __BIT(1) // UnderFlow
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#define FCSR_NX __BIT(0) // iNeXact
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static inline uint32_t
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riscvreg_fcsr_read(void)
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{
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uint32_t __fcsr;
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__asm("frcsr %0" : "=r"(__fcsr));
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return __fcsr;
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}
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static inline uint32_t
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riscvreg_fcsr_write(uint32_t __new)
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{
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uint32_t __old;
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__asm("fscsr %0, %1" : "=r"(__old) : "r"(__new));
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return __old;
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}
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static inline uint32_t
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riscvreg_fcsr_read_fflags(void)
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{
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uint32_t __old;
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__asm("frflags %0" : "=r"(__old));
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return __SHIFTOUT(__old, FCSR_FFLAGS);
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}
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static inline uint32_t
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riscvreg_fcsr_write_fflags(uint32_t __new)
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{
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uint32_t __old;
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__new = __SHIFTIN(__new, FCSR_FFLAGS);
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__asm("fsflags %0, %1" : "=r"(__old) : "r"(__new));
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return __SHIFTOUT(__old, FCSR_FFLAGS);
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}
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static inline uint32_t
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riscvreg_fcsr_read_frm(void)
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{
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uint32_t __old;
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__asm("frrm\t%0" : "=r"(__old));
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return __SHIFTOUT(__old, FCSR_FRM);
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}
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static inline uint32_t
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riscvreg_fcsr_write_frm(uint32_t __new)
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{
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uint32_t __old;
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__new = __SHIFTIN(__new, FCSR_FRM);
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__asm __volatile("fsrm\t%0, %1" : "=r"(__old) : "r"(__new));
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return __SHIFTOUT(__old, FCSR_FRM);
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}
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#define RISCVREG_READ_INLINE(regname) \
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static inline uintptr_t \
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csr_##regname##_read(void) \
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{ \
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uintptr_t __rv; \
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asm volatile("csrr %0, " #regname : "=r"(__rv) :: "memory"); \
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return __rv; \
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}
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#define RISCVREG_WRITE_INLINE(regname) \
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static inline void \
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csr_##regname##_write(uintptr_t __val) \
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{ \
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asm volatile("csrw " #regname ", %0" :: "r"(__val) : "memory"); \
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}
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#define RISCVREG_SET_INLINE(regname) \
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static inline void \
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csr_##regname##_set(uintptr_t __mask) \
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{ \
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if (__builtin_constant_p(__mask) && __mask < 0x20) { \
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asm volatile("csrsi " #regname ", %0" :: "i"(__mask) : \
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"memory"); \
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} else { \
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asm volatile("csrs " #regname ", %0" :: "r"(__mask) : \
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"memory"); \
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} \
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}
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#define RISCVREG_CLEAR_INLINE(regname) \
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static inline void \
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csr_##regname##_clear(uintptr_t __mask) \
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{ \
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if (__builtin_constant_p(__mask) && __mask < 0x20) { \
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asm volatile("csrci " #regname ", %0" :: "i"(__mask) : \
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"memory"); \
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} else { \
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asm volatile("csrc " #regname ", %0" :: "r"(__mask) : \
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"memory"); \
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} \
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}
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#define RISCVREG_READ_WRITE_INLINE(regname) \
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RISCVREG_READ_INLINE(regname) \
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RISCVREG_WRITE_INLINE(regname)
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#define RISCVREG_SET_CLEAR_INLINE(regname) \
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RISCVREG_SET_INLINE(regname) \
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RISCVREG_CLEAR_INLINE(regname)
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#define RISCVREG_READ_SET_CLEAR_INLINE(regname) \
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RISCVREG_READ_INLINE(regname) \
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RISCVREG_SET_CLEAR_INLINE(regname)
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#define RISCVREG_READ_WRITE_SET_CLEAR_INLINE(regname) \
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RISCVREG_READ_WRITE_INLINE(regname) \
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RISCVREG_SET_CLEAR_INLINE(regname)
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/* Supervisor Status Register */
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RISCVREG_READ_SET_CLEAR_INLINE(sstatus) // supervisor status register
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#ifdef _LP64
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#define SR_WPRI __BITS(62, 34) | __BITS(31, 20) | \
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__BIT(17) | __BITS(12, 11) | __BIT(7) | __BITS(4, 2) | \
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__BIT(0)
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#define SR_SD __BIT(63) // any of FS or VS or XS dirty
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/* Bits 62-34 are WPRI */
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#define SR_UXL __BITS(33, 32) // U-mode XLEN
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#define SR_UXL_32 1 // XLEN == 32
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#define SR_UXL_64 2 // XLEN == 64
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#define SR_UXL_128 3 // XLEN == 128
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/* Bits 31-20 are WPRI*/
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#else
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#define SR_WPRI __BITS(30, 20) | \
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__BIT(17) | __BITS(12, 11) | __BIT(7) | __BITS(4, 2) | \
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__BIT(0)
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#define SR_SD __BIT(31) // any of FS or VS or XS dirty
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/* Bits 30-20 are WPRI*/
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#endif /* _LP64 */
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/* Both RV32 and RV64 have the bottom 20 bits shared */
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#define SR_MXR __BIT(19) // Make eXecutable Readable
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#define SR_SUM __BIT(18) // permit Supervisor User Memory access
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/* Bit 17 is WPRI */
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#define SR_XS __BITS(16, 15) // Vector extension state
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#define SR_XS_OFF 0 // All off
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#define SR_XS_SOME_ON 1 // None dirty or clean, some on
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#define SR_XS_SOME_CLEAN 2 // None dirty, some clean
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#define SR_XS_SOME_DIRTY 3 // Some dirty
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#define SR_FS __BITS(14, 13) // Floating-point unit state
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#define SR_FS_OFF 0 // Off
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#define SR_FS_INITIAL 1 // Initial
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#define SR_FS_CLEAN 2 // Clean
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#define SR_FS_DIRTY 3 // Dirty
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/* Bits 12-11 are WPRI */
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#define SR_VS __BITS(10, 9) // User-mode extention state
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#define SR_VS_OFF SR_FS_OFF // Off
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#define SR_VS_INITIAL SR_FS_INITIAL // Initial
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#define SR_VS_CLEAN SR_FS_CLEAN // Clean
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#define SR_VS_DIRTY SR_FS_DIRTY // Dirty
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#define SR_SPP __BIT(8) // Priv level before supervisor mode
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/* Bit 7 is WPRI */
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#define SR_UBE __BIT(6) // User-mode endianness
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#define SR_SPIE __BIT(5) // S-Mode interrupts enabled before trap
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/* Bits 4-2 are WPRI */
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#define SR_SIE __BIT(1) // Supervisor mode interrupt enable
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/* Bit 0 is WPRI */
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/* Supervisor interrupt registers */
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/* ... interrupt pending register (sip) */
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RISCVREG_READ_SET_CLEAR_INLINE(sip) // supervisor interrupt pending
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/* Bit (XLEN-1) - 10 is WIRI */
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#define SIP_SEIP __BIT(9) // S-mode interrupt pending
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/* Bit 8-6 is WIRI */
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#define SIP_STIP __BIT(5) // S-mode timer interrupt pending
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/* Bit 4-2 is WIRI */
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#define SIP_SSIP __BIT(1) // S-mode software interrupt pending
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/* Bit 0 is WIRI */
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/* ... interrupt-enable register (sie) */
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RISCVREG_READ_SET_CLEAR_INLINE(sie) // supervisor interrupt enable
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/* Bit (XLEN-1) - 10 is WIRI */
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#define SIE_SEIE __BIT(9) // S-mode interrupt enable
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/* Bit 8-6 is WIRI */
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#define SIE_STIE __BIT(5) // S-mode timer interrupt enable
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/* Bit 4-2 is WIRI */
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#define SIE_SSIE __BIT(1) // S-mode software interrupt enable
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/* Bit 0 is WIRI */
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/* Mask for all interrupts */
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#define SIE_IM (SIE_SEI |SIE_STIE | SIE_SSIE)
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#ifdef _LP64
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#define SR_USER64 (SR_SPIE | SR_UXL_64) // 64-bit U-mode sstatus
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#define SR_USER32 (SR_SPIE | SR_UXL_32) // 32-bit U-mode sstatus
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#else
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#define SR_USER (SR_SPIE) // U-mode sstatus
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#endif
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// Cause register
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#define CAUSE_INTERRUPT_P(cause) ((cause) & __BIT(XLEN - 1))
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#define CAUSE_CODE(cause) ((cause) & __BITS(XLEN - 2, 0))
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// Cause register - exceptions
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#define CAUSE_FETCH_MISALIGNED 0
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#define CAUSE_FETCH_ACCESS 1
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#define CAUSE_ILLEGAL_INSTRUCTION 2
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#define CAUSE_BREAKPOINT 3
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#define CAUSE_LOAD_MISALIGNED 4
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#define CAUSE_LOAD_ACCESS 5
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#define CAUSE_STORE_MISALIGNED 6
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#define CAUSE_STORE_ACCESS 7
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#define CAUSE_USER_ECALL 8
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#define CAUSE_SYSCALL CAUSE_USER_ECALL /* convenience alias */
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#define CAUSE_SUPERVISOR_ECALL 9
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/* 10 is reserved */
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#define CAUSE_MACHINE_ECALL 11
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#define CAUSE_FETCH_PAGE_FAULT 12
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#define CAUSE_LOAD_PAGE_FAULT 13
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/* 14 is Reserved */
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#define CAUSE_STORE_PAGE_FAULT 15
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/* >= 16 is reserved/custom */
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// Cause register - interrupts
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#define IRQ_SUPERVISOR_SOFTWARE 1
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#define IRQ_MACHINE_SOFTWARE 3
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#define IRQ_SUPERVISOR_TIMER 5
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#define IRQ_MACHINE_TIMER 7
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#define IRQ_SUPERVISOR_EXTERNAL 9
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#define IRQ_MACHINE_EXTERNAL 11
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RISCVREG_READ_INLINE(time)
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#ifdef _LP64
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RISCVREG_READ_INLINE(cycle)
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#else /* !_LP64 */
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static inline uint64_t
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csr_cycle_read(void)
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{
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uint32_t __hi0, __hi1, __lo0;
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do {
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__asm __volatile(
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"csrr\t%[__hi0], cycleh"
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"\n\t" "csrr\t%[__lo0], cycle"
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"\n\t" "csrr\t%[__hi1], cycleh"
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: [__hi0] "=r"(__hi0),
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[__lo0] "=r"(__lo0),
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[__hi1] "=r"(__hi1));
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} while (__hi0 != __hi1);
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return
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__SHIFTIN(__hi0, __BITS(63, 32)) |
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__SHIFTIN(__lo0, __BITS(31, 0));
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}
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#endif /* !_LP64 */
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#ifdef _LP64
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#define SATP_MODE __BITS(63, 60) // Translation mode
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#define SATP_MODE_BARE 0 // No translation or protection
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/* modes 1-7 reserved for standard use */
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#define SATP_MODE_SV39 8 // Page-based 39-bit virt addr
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#define SATP_MODE_SV48 9 // Page-based 48-bit virt addr
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#define SATP_MODE_SV57 10 // Page-based 57-bit virt addr
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#define SATP_MODE_SV64 11 // Page-based 64-bit virt addr
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/* modes 12-13 reserved for standard use */
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/* modes 14-15 designated for custom use */
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#define SATP_ASID __BITS(59, 44) // Address Space Identifier
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#define SATP_PPN __BITS(43, 0) // Physical Page Number
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#else
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#define SATP_MODE __BIT(31) // Translation mode
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#define SATP_MODE_BARE 0 // No translation or protection
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#define SATP_MODE_SV32 1 // Page-based 32-bit virt addr
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#define SATP_ASID __BITS(30, 22) // Address Space Identifier
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#define SATP_PPN __BITS(21, 0) // Physical Page Number
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#endif
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RISCVREG_READ_WRITE_INLINE(satp)
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/* Fake "ASID" CSR (a field of SATP register) functions */
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static inline uint32_t
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csr_asid_read(void)
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{
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uintptr_t satp = csr_satp_read();
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return __SHIFTOUT(satp, SATP_ASID);
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}
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static inline void
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csr_asid_write(uint32_t asid)
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{
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uintptr_t satp = csr_satp_read();
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satp &= ~SATP_ASID;
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satp |= __SHIFTIN(asid, SATP_ASID);
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csr_satp_write(satp);
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}
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#endif /* _RISCV_SYSREG_H_ */ |