48 Commits

Author SHA1 Message Date
Vexu
d312d64c9a stage2: slice types 2020-08-20 16:42:48 -07:00
Vexu
9568248450 stage2: complex pointer types 2020-08-20 16:42:48 -07:00
Vexu
ebfe723f3c stage2: implement rest of simple pointer types 2020-08-20 16:42:48 -07:00
Vexu
ab8a9a6605 stage2: fix astgen of decl ref, add test for global consts 2020-08-19 16:12:29 -07:00
Vexu
e4aefc6d0f
stage2: split ref from lvalue and add compile error for invalid assignments 2020-08-18 22:42:35 +03:00
Vexu
2b45e23477
stage2: character literals and multiline strings 2020-08-18 20:10:18 +03:00
Vexu
e0b01bd4a9
stage2: enum literals 2020-08-18 14:28:33 +03:00
Vexu
7c15c9428e
stage2: array types 2020-08-18 12:36:00 +03:00
Vexu
3eb8f7be10
stage2: astgen bool and/or 2020-08-18 11:38:56 +03:00
Vexu
0977e41407
stage2: ensure discarded error union payload is void 2020-08-18 10:36:57 +03:00
Veikka Tuominen
d8fb377e2a
Merge pull request #6060 from Vexu/stage2
Stage2: more optionals stuff
2020-08-18 00:15:36 +03:00
Vexu
13b2f1e90b
address review feedback 2020-08-17 19:21:03 +03:00
Vexu
ece4a2fc51
stage2: astgen for if and while with error unions 2020-08-17 14:28:04 +03:00
Vexu
db77b6b4e7
stage2: astgen for if and while with optionals 2020-08-17 14:28:04 +03:00
Vexu
012fac255f
stage2: fix optimization causing wrong optional child types 2020-08-17 14:26:32 +03:00
Vexu
c52513e25b
stage2: astgen for ptr types and address of 2020-08-17 14:24:56 +03:00
Noam Preil
3ca8c42e7a
Astgen: further cleanup 2020-08-16 20:36:33 -04:00
Noam Preil
692f38c250
astgen: minor cleanup 2020-08-16 20:32:50 -04:00
Andrew Kelley
66d76cc4f9 stage2: codegen for labeled blocks 2020-08-15 17:03:05 -07:00
Andrew Kelley
0f3f96c850 stage2: astgen for labeled blocks and labeled breaks 2020-08-15 00:52:25 -07:00
Andrew Kelley
f356cba704 stage2: populate some of the astgen switch possibilities
Idea here is simply to entice people to contribute astgen code :)
2020-08-14 22:50:00 -04:00
Andrew Kelley
b49d3672f3 stage2 astgen for LabeledBlock 2020-08-14 22:50:00 -04:00
Andrew Kelley
9a5a1013a8 std.zig.ast: extract out Node.LabeledBlock from Node.Block
This is part of an ongoing effort to reduce size of in-memory AST. This
enum flattening pattern is widespread throughout the self-hosted
compiler.

This is a API breaking change for consumers of the self-hosted parser.
2020-08-14 22:50:00 -04:00
Andrew Kelley
5f7c7191ab stage2: astgen for non-labeled blocks 2020-08-14 11:28:40 -07:00
Andrew Kelley
fc402bdbbb stage2: zir_sema for loops
Also remove the "repeat" instruction and make it implied to be at the
end of a Loop body.
2020-08-13 20:32:32 -07:00
Vexu
6b2ce9d1e9 stage2: split unwrap_optional to safe and unsafe verions 2020-08-13 08:12:17 -07:00
Vexu
4a40282391 stage2: implement unwrap optional 2020-08-13 08:12:17 -07:00
Vexu
5c1fe58613 stage2: gen optional types 2020-08-13 08:12:17 -07:00
Andrew Kelley
de4f3f11f7 stage2: astgen for while loops
See #6021
2020-08-12 21:13:16 -07:00
Andrew Kelley
659603c621 codegen: emit .debug_line ops for IR instructions 2020-08-02 21:28:06 -07:00
Andrew Kelley
64a1a280ef stage2: fix superfluous returnvoid ZIR 2020-07-29 02:29:37 -07:00
Andrew Kelley
5ccee4c986 stage2: more progress towards mutable local variables
* implement sema for runtime deref, store pointer, coerce_to_ptr_elem,
   and store
 * identifiers support being lvalues, except for decls is still TODO
 * codegen supports load, store, ref, alloc
 * introduce more MCValue union tags to support pointers
 * add load, ref, store typed IR instructions
 * add Type.isVolatilePtr
2020-07-29 02:29:36 -07:00
Andrew Kelley
0965724e31 self-hosted: refactor some code out of Module.zig into zir_sema.zig
This makes sense from an organizational point of view, as explained by
this new doc comment at the top of the new file:

//! Semantic analysis of ZIR instructions.
//! This file operates on a `Module` instance, transforming untyped ZIR
//! instructions into semantically-analyzed IR instructions. It does type
//! checking, comptime control flow, and safety-check generation. This is the
//! the heart of the Zig compiler.
//! When deciding if something goes into this file or into Module, here is a
//! guiding principle: if it has to do with (untyped) ZIR instructions, it goes
//! here. If the analysis operates on typed IR instructions, it goes in Module.

Before:
   4009 src-self-hosted/Module.zig

After:
   2776 src-self-hosted/Module.zig
   1128 src-self-hosted/zir_sema.zig

This should be sufficient to avoid the situation we have in stage1 where
ir.cpp is 32,516 lines.
2020-07-27 22:44:18 -07:00
Andrew Kelley
488df7f1d1 stage2: astgen for all arithmetic and assignments 2020-07-27 17:09:47 -07:00
Andrew Kelley
aac6e8c418 self-hosted: AST flattening, astgen improvements, result locations, and more
* AST: flatten ControlFlowExpression into Continue, Break, and Return.
 * AST: unify identifiers and literals into the same AST type: OneToken
 * AST: ControlFlowExpression uses TrailerFlags to optimize storage
   space.
 * astgen: support `var` as well as `const` locals, and support
   explicitly typed locals. Corresponding Module and codegen code is not
   implemented yet.
 * astgen: support result locations.
 * ZIR: add the following instructions (see the corresponding doc
   comments for explanations of semantics):
   - alloc
   - alloc_inferred
   - bitcast_result_ptr
   - coerce_result_block_ptr
   - coerce_result_ptr
   - coerce_to_ptr_elem
   - ensure_result_used
   - ensure_result_non_error
   - ret_ptr
   - ret_type
   - store
   - param_type
 * the skeleton structure for result locations is set up. It's looking
   pretty clean so far.
 * add compile error for unused result and compile error for discarding
   errors.
 * astgen: split builtin calls up to implemented manually, and implement
   `@as`, `@bitCast` (and others) with respect to result locations.
 * add CLI support for hex and raw object formats. They are not
   supported by the self-hosted compiler yet, and emit errors.
 * rename `--c` CLI to `-ofmt=[objectformat]` which can be any of the
   object formats. Only ELF and C are supported so far. Also added missing
   help to the help text.
 * Remove hard tabs from C backend test cases. Shame on you Noam, you
   are grounded, you should know better, etc. Bad boy.
 * Delete C backend code and test case that relied on comptime_int
   incorrectly making it all the way to codegen.
2020-07-23 23:05:26 -07:00
Vexu
c29c79b17a
stage2: remove some dead code, fix build on aarch64 2020-07-21 22:34:14 +03:00
Vexu
da217fadeb
stage2: astgen for floats and other primitive literals 2020-07-21 22:29:28 +03:00
Andrew Kelley
8ee629aa4c stage2: ability for ZIR to map multiple tags to the same type 2020-07-21 12:13:15 -07:00
Andrew Kelley
7a1a924788 stage2: AST: (breaking) flatten out suffix operations 2020-07-21 10:52:24 -07:00
Andrew Kelley
1ac28eed83 stage2 AST: rename OptionalUnwrap to OrElse
preparing to flatten suffix operations AST
2020-07-21 10:46:47 -07:00
Andrew Kelley
1cfe43d563
Merge pull request #5888 from pfgithub/stage-2-testing-Copy
stage2: period and suffixop
2020-07-21 17:42:46 +00:00
Andrew Kelley
ef91b11295 stage2: register allocator processes operand deaths
also rework the IR data structures
2020-07-20 13:12:20 -07:00
pfg
86922b8d08 stage2: support @"identifier" syntax 2020-07-16 14:08:36 -07:00
pfg
83a0073b68 stage2: period and suffixop 2020-07-16 04:22:05 -07:00
Andrew Kelley
d29dd5834b stage2: local consts
These are now supported enough that this example code hits the
limitations of the register allocator:

fn add(a: u32, b: u32) void {
    const c = a + b; // 7
    const d = a + c; // 10
    const e = d + b; // 14
    assert(e == 14);
}
// error: TODO implement copyToNewRegister

So now the next step is to implement register allocation as planned.
2020-07-15 22:36:35 -07:00
Andrew Kelley
af12596e8d stage2: breaking AST memory layout modifications
InfixOp is flattened out so that each operator is an independent AST
node tag. The two kinds of structs are now Catch and SimpleInfixOp.

Beginning implementation of supporting codegen for const locals.
2020-07-15 19:39:18 -07:00
Andrew Kelley
f119092273 stage2: breaking AST memory layout modifications
ast.Node.Id => ast.Node.Tag, matching recent style conventions.

Now multiple different AST node tags can map to the same AST node data
structures. In this commit, simple prefix operators now all map top
SimplePrefixOp.

`ast.Node.castTag` is now preferred over `ast.Node.cast`.

Upcoming: InfixOp flattened out.
2020-07-15 18:15:59 -07:00
Andrew Kelley
e70d6d19f5 stage2: extract AST=>ZIR code to separate file 2020-07-15 15:42:02 -07:00