69 Commits

Author SHA1 Message Date
Jakub Konka
f0d7ec6f33 macho: add x86_64 support 2021-01-13 23:55:37 +01:00
Jakub Konka
7d40aaad2b macho: document more code + add test case 2021-01-13 23:55:18 +01:00
Jakub Konka
b86d0e488b macho: refactor writing and managing externs 2021-01-13 23:55:06 +01:00
Jakub Konka
44a052a65f macho: write out stubs for new externs only 2021-01-13 23:54:46 +01:00
Jakub Konka
f44732c1b0 macho: populate stubs and stub_helper 2021-01-13 23:53:46 +01:00
Jakub Konka
5487dd13ea stage2: lay the groundwork in prep for extern fn
This commit lays the groundwork in preparation for implementing
handling of extern functions in various backends.
2021-01-13 14:51:23 -08:00
joachimschmidt557
a7da90071e stage2: fix bug in genArg
When an argument is unused in the function body, still increment
arg_index so we still select the correct arguments in the args slice.
2021-01-10 00:41:02 -08:00
Andrew Kelley
d7d905696c
Merge pull request #7622 from tetsuo-cpp/array-hash-map-improvements
std: Support equivalent ArrayList operations in ArrayHashMap
2021-01-06 16:32:23 -08:00
joachimschmidt557
be6ac82ee1 stage2 ARM: fix stack offsets for genSetReg and genSetStack 2021-01-06 15:53:10 -08:00
joachimschmidt557
480d6182ad stage2 ARM: fix offsets in exitlude jump relocations 2021-01-06 15:53:10 -08:00
Alex Cameron
d92ea56884 std: Support equivalent ArrayList operations in ArrayHashMap 2021-01-06 00:55:51 +11:00
joachimschmidt557
aa0906e9aa stage2 x86_64: fix bug in Function.gen
Previously, the x86_64 backend would remove code for exitlude relocs
if the jump amount were 0. This causes issues as earlier jumps rely on
the jump being present at the same address.
2021-01-03 19:54:12 -08:00
Jakub Konka
2a410baa2b stage2: implement basic function params aarch64
Implement missing `.register` prong for `aarch64` `genSetReg`.
2021-01-03 23:03:20 +01:00
Andrew Kelley
006e7f6805 stage2: re-use ZIR for comptime and inline calls
Instead of freeing ZIR after semantic analysis, we keep it around so
that it can be used for comptime calls, inline calls, and generic
function calls. ZIR memory is now managed by the Decl arena.

Debug dump() functions are conditionally compiled; only available in
Debug builds of the compiler.

Add a test for an inline function call.
2021-01-02 19:11:55 -07:00
Andrew Kelley
9362f382ab stage2: implement function call inlining in the frontend
* remove the -Ddump-zir thing. that's handled through --verbose-ir
 * rework Fn to have an is_inline flag without requiring any more memory
   on the heap per function.
 * implement a rough first version of dumping typed zir (tzir) which is
   a lot more helpful for debugging than what we had before. We don't
   have a way to parse it though.
 * keep track of whether the inline-ness of a function changes because
   if it does we have to go update callsites.
 * add compile error for inline and export used together.

inline function calls and comptime function calls are implemented the
same way. A block instruction is set up to capture the result, and then
a scope is set up that has a flag for is_comptime and some state if the
scope is being inlined.

when analyzing `ret` instructions, zig looks for inlining state in the
scope, and if found, treats `ret` as a `break` instruction instead, with
the target block being the one set up at the inline callsite.

Follow-up items:
 * Complete out the debug TZIR dumping code.
 * Don't redundantly generate ZIR for each inline/comptime function
   call. Instead we should add a new state enum tag to Fn.
 * comptime and inlining branch quotas.
 * Add more test cases.
2021-01-02 19:11:19 -07:00
LemonBoy
1c13ca5a05 stage2: Use {s} instead of {} when formatting strings 2021-01-02 17:12:57 -07:00
joachimschmidt557
c5ec096b2f stage2 AArch64: add logical (shifted register) instructions 2021-01-01 14:43:12 -08:00
joachimschmidt557
c52ca0b178
stage2 ARM: implement genSetReg with compare_flags 2021-01-01 12:22:16 +01:00
joachimschmidt557
85e1b47c40
stage2 ARM: implement genCondBr for compare_flags 2021-01-01 12:22:16 +01:00
joachimschmidt557
4d2919a1ee
stage2 ARM: implement genCondBr 2021-01-01 12:22:14 +01:00
Andrew Kelley
3f7d9b5fc1 stage2: rework Value Payload layout
This is the same as the previous commit but for Value instead of Type.

Add `Value.castTag` and note that it is preferable to call than
`Value.cast`. This matches other abstractions in the codebase.

Added a convenience function `Value.Tag.create` which really cleans up
the callsites of creating `Value` objects.

`Value` tags can now share payload types. This is in preparation for
another improvement that I want to do.
2020-12-30 21:41:02 -08:00
Andrew Kelley
133da8692e stage2: rework Type Payload layout
Add `Type.castTag` and note that it is preferable to call than
`Type.cast`. This matches other abstractions in the codebase.

Added a convenience function `Type.Tag.create` which really cleans up
the callsites of creating `Type` objects.

`Type` payloads can now share types. This is in preparation for another
improvement that I want to do.
2020-12-30 21:41:02 -08:00
joachimschmidt557
82236a5029
stage2 ARM: implement basic binary bitwise operations 2020-12-21 19:24:21 +01:00
Jakub Konka
2082c27557 stage2+aarch64: clean up offset helper structs 2020-12-09 17:21:21 +01:00
Jakub Konka
e91dbab256 stage2+aarch64: fix stage2 tests 2020-12-09 17:21:17 +01:00
Jakub Konka
eca0727417 stage2+aarch64: use stp and ldp to navigate MachO jump table 2020-12-09 17:20:58 +01:00
Andrew Kelley
ecf7dfcd3a
Merge pull request #7273 from kubkon/lld-codesig-poc
lld+macho: patch lld output on Apple Silicon by calculating and embedding adhoc code signature
2020-12-03 13:41:31 -08:00
Andrew Kelley
463186e856 stage2: wire up -Dskip-non-native
The purpose of this is to save time in the edit-compile-test cycle when
working on stage2 code.
2020-12-02 14:52:56 -07:00
Jakub Konka
1f7fb560ab lld: use commands.LoadCommand in self-hosted linker 2020-12-01 10:49:31 +01:00
joachimschmidt557
2ad2636588
stage2 ARM: use strb + implement genBoolOp 2020-11-28 18:19:22 +01:00
joachimschmidt557
f06f0ebcda
stage2 ARM: Implement genNot 2020-11-28 18:19:22 +01:00
joachimschmidt557
85a3991a43
stage2 codegen: use switch in genBoolOp 2020-11-28 18:19:22 +01:00
joachimschmidt557
27c5c97f21
stage2 ARM: genAdd, genSub for simple cases 2020-11-28 18:19:19 +01:00
Jakub Konka
5ed76268c9 stage2 macho: apply more review comments 2020-11-27 20:55:34 +01:00
Jakub Konka
02baaac506
Update src/codegen.zig
Co-authored-by: Andrew Kelley <andrew@ziglang.org>
2020-11-27 20:31:26 +01:00
Jakub Konka
64eae8f392 stage2 macho: move PIE fixups to link file; fix tests 2020-11-26 11:50:09 +01:00
Jakub Konka
c749b78df5 stage2 macho: add orr and orn instructions 2020-11-26 11:50:09 +01:00
Jakub Konka
10942e3f86 stage2 macho: Hello, Silicon! 2020-11-26 11:50:09 +01:00
Jakub Konka
2cd84b1b3f stage2 macho: refactor PIE generation on x86_64 2020-11-26 11:50:09 +01:00
Jakub Konka
ef5132c508 stage2 macho: first, rough draft at trampolining 2020-11-26 11:50:09 +01:00
Jakub Konka
80b1041c21 stage2 macho: use RIP-relative for memory-set regs x86_64 2020-11-26 11:50:09 +01:00
Tadeo Kondrak
25ec2dbc1e Add builtin.Signedness, use it instead of is_signed 2020-11-19 18:59:21 +02:00
tgschultz
48d60834fd
Move leb128 and remove trivial *mem functions as discussed in #5588 (#6876)
* Move leb128 out of debug and remove trivial *mem functions as discussed in #5588

* Turns out one of the *Mem functions was used by MachO. Replaced with trivial use of FixedBufferStream.
2020-11-16 18:51:54 -05:00
Jakub Konka
a6bc19ea2a stage2 aarch64: add genCall for aarch64 MachO 2020-11-11 14:34:53 +01:00
Jakub Konka
993eb22a77 stage2 aarch64: add .memory prong in genSetReg 2020-11-11 14:34:53 +01:00
joachimschmidt557
ca0016a225 stage2 ARM: start implementing genCall for ELF + genSetReg immediates 2020-11-11 14:34:53 +01:00
joachimschmidt557
4c8f69241a stage2 aarch64: add more instructions 2020-11-11 14:34:53 +01:00
Jakub Konka
4ef6864a15 Add move wide with zero (movz) instruction 2020-11-11 14:34:53 +01:00
Jakub Konka
d601b0f4eb Add basic genSetReg for aarch64 2020-11-11 14:34:53 +01:00
Jakub Konka
d542e88706 Implement genAsm on aarch64
Add remaining PCS info: param and return registers in procedure calls.
2020-11-11 14:34:53 +01:00