329 Commits

Author SHA1 Message Date
Luuk de Gram
ec4c30ae48 wasm: Implement @wasmMemorySize() builtin
This implements the `wasmMemorySize` builtin, in Sema and the Wasm backend.
The Stage2 implementation differs from stage1 in the way that `index` must be a comptime value.
The stage1 variant is incorrect, as the index is part of the instruction encoding, and therefore,
cannot be a runtime value.
2022-03-03 16:33:46 -07:00
Curtis Wilkinson
7fc8dd6642 Zir: rename the 'ret_coerce' tag to 'ret_tok' as per TODO 2022-03-02 14:46:09 -05:00
Cody Tapscott
5c8a507e7a stage2 parser: UTF-8 encode \u{NNNNNN} escape sequences
The core of this change is to re-use the escape sequence parsing logic
for parsing both string and character literals.

The actual fix is that UTF-8 encoding was missing for string literals
with \u{...} escape sequences.
2022-03-02 14:45:19 -05:00
Andrew Kelley
18e42661dc Sema: eliminate use of resolveAlreadyCoercedInt 2022-03-01 14:03:32 -07:00
Veikka Tuominen
7a92b89a9d stage2: forward discard result loc to more expressions 2022-02-27 13:32:55 +02:00
Andrew Kelley
2687b8f7f4 stage2: implement @unionInit
The ZIR instruction `union_init_ptr` is renamed to `union_init`.
I made it always use by-value semantics for now, not taking the time to
invest in result location semantics, in case we decide to change the
rules for unions. This way is much simpler.

There is a new AIR instruction: union_init. This is for a comptime known
tag, runtime-known field value.
vector_init is renamed to aggregate_init, which solves a TODO comment.
2022-02-26 20:59:36 -07:00
Veikka Tuominen
ff72b8a819 stage2: evaluate TypeOf arguments in a separate scope 2022-02-26 18:08:11 +02:00
Andrew Kelley
adb746a701 stage2: improved handling of store_to_block_ptr
* AstGen: remove the setBlockBodyEliding function. This is no longer
   needed after 63788b2a511eb87974065a052e2436b0c6202544.
 * Sema: store_to_block_ptr instruction is handled as
   store_to_inferred_ptr or store, as necessary.
2022-02-24 22:28:37 -07:00
Veikka Tuominen
63788b2a51 stage2: change how stale store_to_block_ptrs are detected
Instead of explicitly setting lhs to .none,
check if the lhs instruction was analyzed.
This simpler approach also handles stores from nested blocks correctly.
2022-02-24 18:32:08 -05:00
Veikka Tuominen
b034c45b2b stage2: implement fieldParentPtr 2022-02-24 19:48:34 +02:00
Andrew Kelley
6249a24e81 stage2: integer-backed packed structs
This implements #10113 for the self-hosted compiler only. It removes the
ability to override alignment of packed struct fields, and removes the
ability to put pointers and arrays inside packed structs.

After this commit, nearly all the behavior tests pass for the stage2 llvm
backend that involve packed structs.

I didn't implement the compile errors or compile error tests yet. I'm
waiting until we have stage2 building itself and then I want to rework
the compile error test harness with inspiration from Vexu's arocc test
harness. At that point it should be a much nicer dev experience to work
on compile errors.
2022-02-23 23:59:25 -07:00
Andrew Kelley
74303a3d95
Merge pull request #10925 from Vexu/stage2
stage2: support anon init through error unions and optionals
2022-02-21 14:18:17 -05:00
Andrew Kelley
bfff8544e1 AstGen: emit break_inline for corresponding inline loops
Prior to this commit there would be a `break` ZIR instruction to break
from a `block_inline` which is a mismatch.
2022-02-19 20:26:57 -07:00
Veikka Tuominen
a2533e6fca stage2: validate struct/array init ty 2022-02-20 02:11:06 +02:00
Andrew Kelley
8841a71aa6 AstGen: evaluate comptime var init expressions in a comptime context 2022-02-19 15:11:18 -07:00
Veikka Tuominen
e027492243 stage2: support anon init through error unions and optionals 2022-02-19 20:21:19 +02:00
Jacob G-W
3bbe6a28e0 stage2: add decltests 2022-02-13 14:42:20 +02:00
Andrew Kelley
7c1061784b stage2: fix inferred comptime constant locals
`const` declarations inside comptime blocks were not getting properly
evaluated at compile-time. To accomplish this there is a new ZIR
instruction, `alloc_inferred_comptime`. Actually we already had one
named that, but it got renamed to `alloc_inferred_comptime_mut` to match
the naming convention with the other similar instructions.
2022-02-08 20:03:17 -07:00
Andrew Kelley
495fd4ee3e AstGen: refactor redundant expressions
This is a non-functional change.
2022-02-06 19:45:49 -07:00
Andrew Kelley
287ff4ab58 stage2: add more float arithmetic and f80 support
AstGen: Fixed bug where f80 types in source were triggering illegal
behavior.

Value: handle f80 in floating point arithmetic functions.

Value: implement floatRem and floatMod

This commit introduces dependencies on compiler-rt that are not
implemented. Those are a prerequisite to merging this branch.
2022-02-06 19:27:54 -07:00
John Schmidt
fd1284ebd0 stage2: apply type coercion in if expressions
When setting the break value in an if expression we must explicitly
check if a result location type coercion that needs to happen. This was
already done for switch expression, so let's just imitate that check
and fix for if expressions. To make this possible, we now also propagate
`rl_ty_inst` to sub scopes.
2022-02-06 21:26:26 -05:00
Andrew Kelley
449554a730 stage2: remove anytype fields from the language
closes #10705
2022-02-01 19:06:40 -07:00
Jakub Konka
627cf6ce48 astgen: clean up source line calculation and management
Clarify that `astgen.advanceSourceCursor` already increments absolute
values of the line and columns numbers; i.e., `GenZir.calcLine` is thus
not only obsolete but wrong by design.

Incidentally, this clean up allows for specifying the `FnDecl` line
numbers for DWARF use correctly as relative values with respect to
the start of the parent `Decl`. This `Decl` in turn has its line number
information specified relatively to its parent `Decl`, and so on, until
we reach the global scope.
2022-01-31 22:29:29 -05:00
Veikka Tuominen
a31a749c42 stage1: add f80 type 2022-01-28 11:45:04 -07:00
Andrew Kelley
50accb757f stage2: fix crash on file-level struct field source locations 2022-01-26 20:02:01 -07:00
Andrew Kelley
a2abbeef90 stage2: rework a lot of stuff
AstGen:
 * rename the known_has_bits flag to known_non_opv to make it better
   reflect what it actually means.
 * add a known_comptime_only flag.
 * make the flags take advantage of identifiers of primitives and the
   fact that zig has no shadowing.
 * correct the known_non_opv flag for function bodies.

Sema:
 * Rename `hasCodeGenBits` to `hasRuntimeBits` to better reflect what it
   does.
   - This function got a bit more complicated in this commit because of
     the duality of function bodies: on one hand they have runtime bits,
     but on the other hand they require being comptime known.
 * WipAnonDecl now takes a LazySrcDecl parameter and performs the type
   resolutions that it needs during finish().
 * Implement comptime `@ptrToInt`.

Codegen:
 * Improved handling of lowering decl_ref; make it work for
   comptime-known ptr-to-int values.
   - This same change had to be made many different times; perhaps we
     should look into merging the implementations of `genTypedValue`
     across x86, arm, aarch64, and riscv.
2022-01-24 21:53:57 -07:00
Andrew Kelley
b34f994c0b stage2: type system treats fn ptr and body separately
This commit updates stage2 to enforce the property that the syntax
`fn()void` is a function *body* not a *pointer*. To get a pointer, the
syntax `*const fn()void` is required.

ZIR puts function alignment into the func instruction rather than the
decl because this way it makes it into function types. LLVM backend
respects function alignments.

Struct and Union have methods `fieldSrcLoc` to help look up source
locations of their fields. These trigger full loading, tokenization, and
parsing of source files, so should only be called once it is confirmed
that an error message needs to be printed.

There are some nice new error hints for explaining why a type is
required to be comptime, particularly for structs that contain function
body types.

`Type.requiresComptime` is now moved into Sema because it can fail and
might need to trigger field type resolution. Comptime pointer loading
takes into account types that do not have a well-defined memory layout
and does not try to compute a byte offset for them.

`fn()void` syntax no longer secretly makes a pointer. You get a function
body type, which requires comptime. However a pointer to a function body
can be runtime known (obviously).

Compile errors that report "expected pointer, found ..." are factored
out into convenience functions `checkPtrOperand` and `checkPtrType` and
have a note about function pointers.

Implemented `Value.hash` for functions, enum literals, and undefined values.

stage1 is not updated to this (yet?), so some workarounds and disabled
tests are needed to keep everything working. Should we update stage1 to
these new type semantics? Yes probably because I don't want to add too
much conditional compilation logic in the std lib for the different
backends.
2022-01-24 21:47:53 -07:00
Andrew Kelley
8a69726209 AstGen: doc comment fixups
* AstGen: use Ast.zig helper methods to avoid copy pasting token counting logic
   - take advantage of the `first_doc_comment` field we already have for
     param AST nodes
 * Add missing ZIR docs
2022-01-23 16:24:46 -07:00
Loris Cro
ba55e32ef2 add function param doc comment info in zir 2022-01-21 22:00:57 +01:00
Loris Cro
1f56ff8343 add support for more decl attributes in doc comment zir
The previous commit that implemented doc comment zir support for
decls did not properly account for all the possible attribute
keyword combinations (threadlocal, extern, and such).
2022-01-21 22:00:57 +01:00
Loris Cro
98fddd1c54 add field doc comments to zir
Doc comment information is stored in `extra` unconditionally for
each field. This commmit covers Structs, Enums, Unions, and ErrSets.
2022-01-21 22:00:57 +01:00
Loris Cro
3010ccfca5 astgen saves decl doc comments in zir
The field is saved in `extra` unconditionally for each decl.
2022-01-21 22:00:56 +01:00
Andrew Kelley
e86ff712a6 stage2: implement tuples
* AIR instruction vector_init gains the ability to init arrays and
   tuples in addition to vectors. This will probably also gain the
   ability to initialize structs and be renamed to `aggregate_init`.
 * AstGen prefers to use an `anon_array_init` ZIR instruction for
   local variables when the init expr is an array literal and there is
   no type.
2022-01-20 16:17:16 -07:00
Andrew Kelley
84c2c47fae Sema: implement else capture value
The ZIR instructions `switch_capture_else` and `switch_capture_ref` are
removed because they are not needed. Instead, the prong index is set to
max int for the special prong.

Else prong with error sets is not handled yet.

Adds a new behavior test because there was not a prior on to cover only
the capture value of else on a switch.
2022-01-17 20:45:55 -07:00
riverbl
c71cf48cb5 stage2: do not interpret identifier containing underscores (eg: u3_2) as int primitive type 2022-01-17 16:54:48 +02:00
Andrew Kelley
7f41e20802 AstGen: emit as instructions for branching expressions
There is a mechanism to avoid redundant `as` ZIR instructions which is
to pass `ResultLoc.coerced_ty` instead of `ResultLoc.ty` when it is
known by AstGen that Sema will do the coercion.

This commit downgrades `coerced_ty` to `ty` when a result location
passes through an expression that branches, such as `if`, `switch`,
`while`, and `for`, causing the `as` ZIR instruction to be emitted.

This ensures that the type of a result location will be applied to, e.g.
a `comptime_int` on either side of a branch on a runtime condition.
2022-01-15 23:13:44 -07:00
Andrew Kelley
336d0c97fe stage2: detection of comptime array literals
Introduce `validate_array_init_comptime`, similar to
`validate_struct_init_comptime` introduced in
713d2a9b3883942491b40738245232680877cc66.

`zirValidateArrayInit` is improved to detect comptime array literals and
emit AIR accordingly. This code is very similar to the changes
introduced in that same commit for `zirValidateStructInit`.

The C backend needed some improvements to continue passing the same set
of tests:
 * `resolveInst` for arrays now will add a local `static const` with the
   array value and so then `elem_val` instructions reference that local.
   It memoizes accesses using `value_map`, which is changed to use
   `Air.Inst.Ref` as the key rather than `Air.Inst.Index`.
 * This required a mechanism for writing to a "header" which is lines
   that appear at the beginning of a function body, before everything
   else.
 * dbg_stmt output comments rather than `#line` directives.
   TODO comment reproduced here:

We need to re-evaluate whether to emit these or not. If we naively emit
these directives, the output file will report bogus line numbers because
every newline after the #line directive adds one to the line.
We also don't print the filename yet, so the output is strictly unhelpful.
If we wanted to go this route, we would need to go all the way and not output
newlines until the next dbg_stmt occurs.
Perhaps an additional compilation option is in order?

`Value.elemValue` is improved to support `elem_ptr` values.
2022-01-13 22:13:44 -07:00
Andrew Kelley
93b854eb74 stage2: implement @ctz and @clz including SIMD
AIR:
 * `array_elem_val` is now allowed to be used with a vector as the array
   type.
 * New instructions: splat, vector_init

AstGen:
 * The splat ZIR instruction uses coerced_ty for the ResultLoc, avoiding
   an unnecessary `as` instruction, since the coercion will be performed
   in Sema.
 * Builtins that accept vectors now ignore the type parameter. Comment
   from this commit reproduced here:

   The accepted proposal #6835 tells us to remove the type parameter from
   these builtins. To stay source-compatible with stage1, we still observe
   the parameter here, but we do not encode it into the ZIR. To implement
   this proposal in stage2, only AstGen code will need to be changed.

Sema:
 * `clz` and `ctz` ZIR instructions are now handled by the same function
   which accept AIR tag and comptime eval function pointer to
   differentiate.
 * `@typeInfo` for vectors is implemented.
 * `@splat` is implemented. It takes advantage of `Value.Tag.repeated` 😎
 * `elemValue` is implemented for vectors, when the index is a scalar.
   Handling a vector index is still TODO.
 * Element-wise coercion is implemented for vectors. It could probably
   be optimized a bit, but it is at least complete & correct.
 * `Type.intInfo` supports vectors, returning int info for the element.
 * `Value.ctz` initial implementation. Needs work.
 * `Value.eql` is implemented for arrays and vectors.

LLVM backend:
 * Implement vector support when lowering `array_elem_val`.
 * Implement vector support when lowering `ctz` and `clz`.
 * Implement `splat` and `vector_init`.
2022-01-12 23:53:26 -07:00
Robin Voetter
cc5c25d48b stage2: implement @src 2022-01-08 14:32:40 -05:00
Andrew Kelley
713d2a9b38 Sema: better code generated for struct literals
Add a variant of the `validate_struct_init` ZIR instruction:
`validate_struct_init_comptime` which is the same thing except it
indicates a comptime scope.

Sema code for this instruction now handles default struct field
values and detects when the struct initialization resulted in a
comptime value, replacing the already-emitted AIR instructions
to store each individual field with a single `store` instruction
with a comptime struct value as the operand.

In the case of a comptime scope, there is a simpler path that only
evals the implicit store instructions for default field values, avoiding
the mechanism for detecting comptime values.

This regressed one test case for the wasm backend, but it's just hitting
a different prong of `emitConstant` which currently has "TODO" in there,
so I think it's fine.
2022-01-04 23:49:49 -07:00
Jarred Sumner
2d9508780a For unused references & redundant keywords, append the compiler error but continue running AstGen 2021-12-30 22:45:43 -05:00
Andrew Kelley
70894d5c2f AstGen: fix loop result locations
The main problem was that the loop body was treated as an expression
that was one of the peer result values of a loop, when in reality the
loop body is noreturn and only the `break` operands are the result
values of loops.

This was solved by introducing an override that prevents rvalue() from
emitting a store to result location instruction for loop bodies.

An orthogonal change also included in this commit is switching
`elem_val` index expressions to using `coerced_ty` and doing the
coercion to `usize` inside `Sema`, resulting in smaller ZIR (since the
cast becomes implied).

I also changed the break operand expression to use `reachableExpr`,
introducing a new compile error for double break.

This makes a few more behavior tests pass for `while` and `for` loops.
2021-12-27 15:30:31 -07:00
Robin Voetter
e18c3f3109 stage2: wrap function prototypes in an inline block.
Previously, function parameter instructions for function prototypes would be
generated in the parent block. This caused issues in blocks where multiple
prototypes would be generated in, such as the block for struct fields for
example. This change introduces an inline block around every prototype such
that all parameters for a prototype are confined to a unique block.
2021-12-21 01:41:50 +01:00
Isaac Freund
9f9f215305
stage1, stage2: rename c_void to anyopaque (#10316)
zig fmt now replaces c_void with anyopaque to make updating
code easy.
2021-12-19 00:24:45 -05:00
Isaac Freund
175463d75d
AstGen: implement @prefetch() builtin 2021-12-10 23:09:02 +01:00
Isaac Freund
47c309c34a
AstGen: increase zig fmt off/on granularity
This enables automatic formatting for a significant amount of code that
currently doesn't deviate from the standard zig fmt enforced style.
2021-12-10 23:09:01 +01:00
Andrew Kelley
cbd653e1d6 AstGen: expr-evaluate asm template expressions
See previous commit 1912ec0323af9a9077a8706157beb8207f6e3eb9 for more
context.

closes #10262
2021-12-02 14:35:35 -07:00
Andrew Kelley
1912ec0323 AstGen: use null string to communicate non-string-literal asm
dd62a6d2e8de522187fd096354e7156cca1821c5 short-circuited the logic of
`asmExpr` by emitting ZIR for `@compileError("...")`. This caused false
positive "unreachable code" errors for stage1 when there was an
expression in the asm template.

This commit makes such cases instead go through logic of `asmExpr` like
normal, however the asm template is set to 0. This is then picked up in
Sema (part of stage2, not stage1) and reported as "assembly code must
use string literal syntax".
2021-12-01 16:24:44 -07:00
Andrew Kelley
7355a20133
Merge pull request #10055 from leecannon/allocator_refactor
Allocgate
2021-11-30 18:48:31 -08:00
Andrew Kelley
dd62a6d2e8 AstGen: allow non-string-literal inline assembly for stage1
The end-game for inline assembly is that the syntax is more integrated
with zig, and it will not allow string concatenation for the assembler
code, for the same reasons that Zig does not have a preprocessor.

However, inline assembly in zig right now is lacking for a variety of
use cases (take a look at the open issues having to do with inline
assembly for example), and being able to use comptime expressions to
concatenate text is a workaround that real-world users are exploiting to
get by in the short term.

This commit keeps "assembly code must use string literal syntax" as a
compile error when using stage2, but allows it through when using
stage1.

I expect to revert this commit after making enough improvements to
inline assembly that our real world users' needs are satisfied.
2021-11-30 19:45:08 -07:00