242 Commits

Author	SHA1	Message	Date
David Rubin	8da212c11b	riscv: update tests and fix reuse bug	2024-07-26 04:19:58 -07:00
David Rubin	a1f6a8ef90	riscv: airAsm rewrite ... with this rewrite we can call functions inside of inline assembly, enabling us to use the default start.zig logic all that's left is to implement lr/sc loops for atomically manipulating 1 and 2 byte values, after which we can use the segfault handler logic.	2024-07-26 04:19:55 -07:00
David Rubin	b533e848a2	riscv: enable passing tests	2024-07-26 04:19:17 -07:00
David Rubin	c00a5ff792	riscv: implement @floatFromInt	2024-07-26 04:19:16 -07:00
David Rubin	cde6956b21	riscv: remove redundant assert in genBinOp	2024-07-26 04:05:41 -07:00
David Rubin	8d30fc45c4	riscv: implement more operators ... we can run `std.debug.print` now, with both run-time strings and integers!	2024-07-26 04:05:39 -07:00
David Rubin	e60c581147	test: disable-enable riscv tests	2024-06-13 04:42:26 -07:00
David Rubin	3967e00047	riscv: disable failing test	2024-06-13 02:24:39 -07:00
David Rubin	4fd8900337	riscv: rewrite "binOp" ... Reorganize how the binOp and genBinOp functions work. I've spent quite a while here reading exactly through the spec and so many tests are enabled because of several critical issues the old design had. There are some regressions that will take a long time to figure out individually so I will ignore them for now, and pray they get fixed by themselves. When we're closer to 100% passing is when I will start diving into them one-by-one.	2024-06-13 02:24:39 -07:00
David Rubin	a270c6f8c8	riscv: implement optional logic	2024-06-13 02:22:33 -07:00
David Rubin	d69c48370a	riscv: integer + float @abs	2024-06-13 02:22:06 -07:00
David Rubin	c10d1c6a75	riscv: implement more arithmetic instructions	2024-06-13 02:22:05 -07:00
David Rubin	083b7b483e	riscv: zero registers when using register-wide operations ... what was happening is that instructions like `lb` were only affecting the lower bytes of the register and leaving the top dirty. this would lead to situtations were `cmp_eq` for example was using `xor`, which was failing because of the left-over stuff in the top of the register. with this commit, we now zero out or truncate depending on the context, to ensure instructions like xor will provide proper results.	2024-06-13 02:22:04 -07:00
David Rubin	7ed2f2156f	riscv: fix register clobber in certain edge cases	2024-06-13 02:21:38 -07:00
David Rubin	05de6c279b	riscv: std.fmt.format running ... - implements `airSlice`, `airBitAnd`, `airBitOr`, `airShr`. - got a basic design going for the `airErrorName` but for some reason it simply returns empty bytes. will investigate further. - only generating `.got.zig` entries when not compiling an object or shared library - reduced the total amount of ops a mnemonic can have to 3, simplifying the logic	2024-06-13 02:20:47 -07:00
David Rubin	c457f35da5	riscv: arbitrary sized arrays	2024-06-13 02:19:40 -07:00
David Rubin	004d0c8978	riscv: switch progress + by-ref return progress	2024-06-13 02:19:38 -07:00
Robin Voetter	b9d738a5cf	spirv: disable tests that fail on pocl ... Besides the Intel OpenCL CPU runtime, we can now run the behavior tests using the Portable Computing Language. This implementation is open-source, so it will be easier for us to patch in updated versions of spirv-llvm-translator that have bug fixes etc.	2024-06-10 20:32:34 +02:00
David Rubin	ffb63a05a3	riscv: finally fix bug + airAggregateInit ... i just hadn't realized that I placed the `riscv_start` branch in the non-simplified starts	2024-05-11 02:17:24 -07:00
David Rubin	2fd83d8c0a	riscv: by-value structs + @min	2024-05-11 02:17:24 -07:00
David Rubin	a30af172e8	riscv: math progress	2024-05-11 02:17:24 -07:00
David Rubin	d9e0cafe64	riscv: add stage2_riscv to test matrix and bypass failing tests	2024-05-11 02:17:24 -07:00
Andrew Kelley	badc28c06e	disable regressed test from LLVM 18 upgrade ... tracked by #19825	2024-05-08 19:37:29 -07:00
Jacob Young	f1c0f42cdd	cbe: fix optional codegen ... Also reduce ctype pool string memory usage, remove self assignments, and enable more warnings.	2024-04-13 01:35:20 -04:00
Robin Voetter	2f9e37ade0	spirv: enable passing tests	2024-03-18 19:13:51 +01:00
Robin Voetter	4020b91f21	spirv: skip test that miscompiles on Intel	2024-03-18 19:13:51 +01:00
garrison hinson-hasty	1e67f50211	Sema: fix compiler crash @ptrCasting optional slice	2024-03-05 18:55:21 +00:00
Jacob Young	2fcb2f5975	Sema: implement vector coercions ... These used to be lowered elementwise in air, and now are a single air instruction that can be lowered elementwise in the backend if necessary.	2024-02-25 11:22:10 +01:00
Jacob Young	2fdc9e6ae8	x86_64: implement @shuffle	2024-02-25 11:22:10 +01:00
garrison hinson-hasty	955fd65cb1	Sema: fix peer type resolution for arrays of coercible elements	2024-02-21 00:55:29 +00:00
Ali Chraghi	37b0aa600a	spirv: make rusticl the primary testing implementation	2024-02-09 09:27:08 +03:30
Jakub Konka	52066bf8e4	x86_64+macho: pass more behavior tests	2024-02-06 19:01:17 +01:00
Robin Voetter	9fbba0e01a	spirv: update tests	2024-02-04 19:09:33 +01:00
Robin Voetter	76d5696434	spirv: air abs	2024-02-04 19:09:32 +01:00
Robin Voetter	631d1b63a8	spirv: fix shuffle properly	2024-02-04 19:09:32 +01:00
Robin Voetter	408c117246	spirv: air is_(non_)null_ptr, optional_payload_ptr	2024-02-04 19:09:30 +01:00
Robin Voetter	345d6e280d	spirv: air int_from_bool	2024-02-04 19:09:29 +01:00
David Rubin	100efcf8d3	return optional state to zirPtrCastNoDest	2024-01-19 21:25:05 +02:00
dweiller	8108c9f4d2	test/behavior: replace all 'comptime expect' with 'comptime assert'	2024-01-15 20:55:01 +11:00
Veikka Tuominen	804cee3b93	categorize behavior/bugs/<issueno>.zig tests	2024-01-06 16:49:41 -08:00
Carl Åstholm	85869f8225	Correct expected/actual parameter order of some assertions	2024-01-03 21:20:49 +01:00
Carl Åstholm	4c1da0912a	Fix compile errors from the expectEqual change	2024-01-03 21:20:48 +01:00
Jacob Young	50993a8f08	x86_64: implement more operations on vectors with 1-bit elements	2023-12-04 01:29:07 -05:00
Jacob Young	485e20884c	x86_64: implement movement for pointer vectors	2023-12-03 23:07:50 -05:00
Jacob Young	7c85ea65ba	x86_64: "implement" aggregate_init for vectors	2023-12-03 13:55:31 -05:00
Jacob Young	e00f1397e3	x86_64: implement some todos	2023-12-03 10:24:03 -05:00
mlugg	3c585730f2	AstGen: preserve result type in comptime block	2023-11-19 11:11:50 +00:00
mlugg	9c16b2370d	test: update behavior to silence 'var is never mutated' errors	2023-11-19 09:57:03 +00:00
mlugg	d78eda34c5	Sema: emit @intCast safety check correctly for vectors ... This code was previously tripping an assertion by not making this value used in the safety check a vector.	2023-11-07 06:42:15 +00:00
Andrew Kelley	3fc6fc6812	std.builtin.Endian: make the tags lower case ... Let's take this breaking change opportunity to fix the style of this enum.	2023-10-31 21:37:35 -04:00