15117 Commits

Author SHA1 Message Date
Alex Rønne Petersen
b49b7501cf
std.Target: Remove cloudabi OS tag.
It's discontinued in favor of WASI.

https://github.com/NuxiNL/cloudlibc
2024-07-30 06:30:26 +02:00
Alex Rønne Petersen
ef06e4b6e4
std.Target: Remove ananas OS tag.
This is a fairly small hobby OS that has not seen development in 2 years. Our
current policy is that hobby OSs should use the `other` tag.

https://github.com/zhmu/ananas
2024-07-30 06:30:25 +02:00
Alex Rønne Petersen
c8ca05e93a
std.Target: Remove sparcel architecture tag.
What is `sparcel`, you might ask? Good question!

If you take a peek in the SPARC v8 manual, §2.2, it is quite explicit that SPARC
v8 is a big-endian architecture. No little-endian or mixed-endian support to be
found here.

On the other hand, the SPARC v9 manual, in §3.2.1.2, states that it has support
for mixed-endian operation, with big-endian mode being the default.

Ok, so `sparcel` must just be referring to SPARC v9 running in little-endian
mode, surely?

Nope:

* 40b4fd7a3e/llvm/lib/Target/Sparc/SparcTargetMachine.cpp (L226)
* 40b4fd7a3e/llvm/lib/Target/Sparc/SparcTargetMachine.cpp (L104)

So, `sparcel` in LLVM is referring to some sort of fantastical little-endian
SPARC v8 architecture. I've scoured the internet and I can find absolutely no
evidence that such a thing exists or has ever existed. In fact, I can find no
evidence that a little-endian implementation of SPARC v9 ever existed, either.
Or any SPARC version, actually!

The support was added here: https://reviews.llvm.org/D8741

Notably, there is no mention whatsoever of what CPU this might be referring to,
and no justification given for the "but some are little" comment added in the
patch.

My best guess is that this might have been some private exercise in creating a
little-endian version of SPARC that never saw the light of day. Given that SPARC
v8 explicitly doesn't support little-endian operation (let alone little-endian
instruction encoding!), and no CPU is known to be implemented as such, I think
it's very reasonable for us to just remove this support.
2024-07-30 06:30:25 +02:00
Alex Rønne Petersen
1e9278d718
std.Target: Remove spir/spir64 architecture tags.
These were for very old OpenCL have been long abandoned in favor of SPIR-V.

* https://github.com/KhronosGroup/SPIR
* https://github.com/KhronosGroup/SPIR-Tools
2024-07-30 06:30:25 +02:00
Andrew Kelley
38e0f049c5
Merge pull request #20389 from alexrp/riscv32
Some `riscv32-linux` porting work
2024-07-29 16:13:35 -07:00
Andrew Kelley
19e4de135f
Merge pull request #20839 from alexrp/musl-stuff
`musl`: Align `CFLAGS` with upstream
2024-07-29 11:34:18 -07:00
Alex Rønne Petersen
27507ad971 compiler: Enable -Werror=date-time for C/C++ code in release builds.
We advertise reproducible builds for release modes, so let's help users achieve
that in C/C++ code. Users can still override this manually if they really want.
2024-07-29 11:27:38 -07:00
Alex Rønne Petersen
6ec7757914
link.Elf: Define __global_pointer$ for riscv32 too.
See: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc
2024-07-29 09:50:09 +02:00
Alex Rønne Petersen
11badbfe8e
musl: Fix needsCrtiCrtn() to return false for riscv32 too. 2024-07-29 09:50:09 +02:00
Alex Rønne Petersen
d1d95294fd std.Target.Cpu.Arch: Remove the aarch64_32 tag.
This is a misfeature that we inherited from LLVM:

* https://reviews.llvm.org/D61259
* https://reviews.llvm.org/D61939

(`aarch64_32` and `arm64_32` are equivalent.)

I truly have no idea why this triple passed review in LLVM. It is, to date, the
*only* tag in the architecture component that is not, in fact, an architecture.
In reality, it is just an ILP32 ABI for AArch64 (*not* AArch32).

The triples that use `aarch64_32` look like `aarch64_32-apple-watchos`. Yes,
that triple is exactly what you think; it has no ABI component. They really,
seriously did this.

Since only Apple could come up with silliness like this, it should come as no
surprise that no one else uses `aarch64_32`. Later on, a GNU ILP32 ABI for
AArch64 was developed, and support was added to LLVM:

* https://reviews.llvm.org/D94143
* https://reviews.llvm.org/D104931

Here, sanity seems to have prevailed, and a triple using this ABI looks like
`aarch64-linux-gnu_ilp32` as you would expect.

As can be seen from the diffs in this commit, there was plenty of confusion
throughout the Zig codebase about what exactly `aarch64_32` was. So let's just
remove it. In its place, we'll use `aarch64-watchos-ilp32`,
`aarch64-linux-gnuilp32`, and so on. We'll then translate these appropriately
when talking to LLVM. Hence, this commit adds the `ilp32` ABI tag (we already
have `gnuilp32`).
2024-07-28 19:44:52 -07:00
Alex Rønne Petersen
c157550928 link.Coff: Basic support for /Brepro in the self-hosted linker.
Just keep things simple and zero the timestamp. It's not obvious that there's
any real benefit to adding complexity and harming performance by computing a
hash of the whole file for the timestamp value.

See:

* https://learn.microsoft.com/en-us/windows/win32/debug/pe-format#general-concepts
* https://learn.microsoft.com/en-us/windows/win32/debug/pe-format#debug-type

In the future, we should at least add an empty `IMAGE_DEBUG_TYPE_REPRO` entry to
the debug data directory for this case, but I didn't want to do too much surgery
right now since it's early days for COFF support in the self-hosted linker.
2024-07-28 22:49:41 +02:00
Alex Rønne Petersen
b03a04c7fc
musl: Build with -fexcess-precision=standard -frounding-math.
Clang supports these now.
2024-07-28 15:42:02 +02:00
Alex Rønne Petersen
243bb87db0
musl: Build with -fno-strict-aliasing like upstream. 2024-07-28 15:41:35 +02:00
Alex Rønne Petersen
642cd730c8 link: Accept -Brepro linker option and pass it to LLD.
Enable it by default when building Zig code in release modes.

Contributes to #9432.
2024-07-28 14:37:03 +02:00
Jakub Konka
91c17979f1
Merge pull request #20807 from Rexicon226/riscv
riscv: more backend progress
2024-07-28 11:34:23 +02:00
Jakub Konka
1fba9e1280
Merge pull request #20834 from ziglang/macho-boundary-typo-fix
macho: fix typo in boundary symbols handling
2024-07-28 10:30:26 +02:00
Linus Groh
a84951465b translate-c: Use mangled name for local extern in condition/loop 2024-07-28 02:58:49 +03:00
Jakub Konka
77476a03e8 macho: fix typo in boundary symbol tag: $stop -> $end 2024-07-27 23:56:18 +02:00
David Rubin
b20007daf7
riscv: correct airAsm to generate correct jalr call 2024-07-27 08:14:09 -07:00
David Rubin
8f84212855
riscv: make multi-threaded enabled compilation the default 2024-07-26 14:53:55 -07:00
David Rubin
a7498a6a53
comp: enable compilation of zig_libc 2024-07-26 14:02:48 -07:00
David Rubin
846bd40361
riscv: implement @cmpxchg* and remove fixes 2024-07-26 12:43:47 -07:00
David Rubin
9752bbfeb3
riscv: implement basic tlv loads and stores 2024-07-26 08:49:34 -07:00
Andrew Kelley
208baa37ca frontend: add missed cache hash on --debug-rt
Makes adding --debug-rt correctly invalidate the cache for compiler_rt
and libfuzzer.
2024-07-26 08:42:40 -07:00
Andrew Kelley
80269c1f53 remove deprecated --mod CLI now that a zig1.wasm update happened 2024-07-26 05:07:18 -07:00
David Rubin
8da212c11b
riscv: update tests and fix reuse bug 2024-07-26 04:19:58 -07:00
David Rubin
046001a34a
riscv implement @popCount 2024-07-26 04:19:57 -07:00
David Rubin
7ff5709e1b
riscv: implement lr/sr loop logic for non-native atomics 2024-07-26 04:19:57 -07:00
David Rubin
a1f6a8ef90
riscv: airAsm rewrite
with this rewrite we can call functions inside of
inline assembly, enabling us to use the default start.zig logic

all that's left is to implement lr/sc loops for atomically manipulating
1 and 2 byte values, after which we can use the segfault handler logic.
2024-07-26 04:19:55 -07:00
David Rubin
c00a5ff792
riscv: implement @floatFromInt 2024-07-26 04:19:16 -07:00
David Rubin
1a7d89a84d
riscv: clean up and unify encoding logic 2024-07-26 04:19:13 -07:00
David Rubin
574028ed5e
riscv: boilerplate for creating lazy functions 2024-07-26 04:05:44 -07:00
David Rubin
64c6473443
riscv: implement add_sat and ptr_slice_len_ptr
this is enough to use the basic functions of an ArrayList!
2024-07-26 04:05:43 -07:00
David Rubin
6ac1b2d82a
riscv: add 32-bit support to integer @abs 2024-07-26 04:05:42 -07:00
David Rubin
1820f44104
riscv: implement sub-byte addition 2024-07-26 04:05:42 -07:00
David Rubin
81ca3a1d59
riscv: fix logic bug in ptr_elem_ptr
I was doing duplicate work with `elemOffset` multiplying by the abi size and then the `ptr_add` `genBinOp` also multiplying.

This led to having writes happening in the wrong place.
2024-07-26 04:05:41 -07:00
David Rubin
cde6956b21
riscv: remove redundant assert in genBinOp 2024-07-26 04:05:41 -07:00
David Rubin
d3f75522d7
lower: fix logic bug in cmp_gt 2024-07-26 04:05:40 -07:00
David Rubin
c78ebeb44c
riscv: implement ptr_slice_ptr_ptr
just one step closer to allocation
2024-07-26 04:05:40 -07:00
David Rubin
93e9c7a963
riscv: implement @clz 2024-07-26 04:05:39 -07:00
David Rubin
8d30fc45c4
riscv: implement more operators
we can run `std.debug.print` now, with both run-time strings and integers!
2024-07-26 04:05:39 -07:00
David Rubin
9766b68c47
riscv: un-cache the avl and vtype when returning from a function call
the csrs `avl` and `vtype` are considered caller-saved so it could have changed while inside of the function.
the easiest way to handle this is to just set the cached `vtype` and `avl` to null, so that the next time something
needs to set it, it'll emit an instruction instead of relying on a potentially invalid setting.
2024-07-26 04:05:38 -07:00
Alex Rønne Petersen
9536d65230 main: Don't pass --seed for zig run. 2024-07-25 19:30:13 -07:00
Andrew Kelley
a3c74aca99 add --debug-rt CLI arg to the compiler + bonus edits
The flag makes compiler_rt and libfuzzer be in debug mode.

Also:
* fuzzer: override debug logs and disable debug logs for frequently
  called functions
* std.Build.Fuzz: fix bug of rerunning the old unit test binary
* report errors from rebuilding the unit tests better
* link.Elf: additionally add tsan lib and fuzzer lib to the hash
2024-07-25 18:52:21 -07:00
Andrew Kelley
3256df2ff8 llvm: always include instrumentation function attributes 2024-07-25 18:52:20 -07:00
Alex Rønne Petersen
1c35e73b61 llvm: Don't emit safety memset() for stores of undef in Debug with safety off.
Before, this code:

    @setRuntimeSafety(false);
    var arr: [38]elf.Addr = undefined;

would emit a call to memset() in the output code in Debug mode, while in all the
release modes, LLVM optimized the memset() out as expected. Emitting the call in
Debug mode is problematic in some contexts, e.g. in std.os.linux.start_pie where
we are not yet ready to correctly perform calls because relocations haven't been
applied yet, or in the early stages of a dynamic linker, etc.
2024-07-25 18:04:50 -07:00
Andrew Kelley
b22357b88b
Merge pull request #20783 from ziglang/cache-fix
build compiler_rt and fuzzer in parallel; fix false positive cache hits
2024-07-25 07:12:39 -07:00
Jacob Young
18685e928d main: avoid sending an empty file system inputs message
When all compiler inputs are invalid paths, there could be errors yet no
valid file system inputs.

Closes #20713
2024-07-25 03:59:30 -07:00
Andrew Kelley
94f4f9c4ef add sub-compilation cache inputs to parents in whole mode
closes #20782
2024-07-24 19:40:54 -07:00
Andrew Kelley
4135cc9d0b CLI: better error message when build runner cannot be spawned 2024-07-24 19:40:38 -07:00