246 Commits

Author SHA1 Message Date
Jacob Young
2770159606 std: reenable vectorized code with the C backend 2023-03-06 08:09:32 -05:00
Andrew Kelley
aeaef8c0ff update std lib and compiler sources to new for loop syntax 2023-02-18 19:17:21 -07:00
Andrew Kelley
2f5892671e move compiler's CType logic to std.Target
This API only depends on std.Target and is extremely useful in build
scripts when populating configure files.
2023-01-31 15:09:35 -07:00
Andrew Kelley
d6b430b520 std.Target: remove workaround
This was working around a stage1 compiler bug.
2023-01-31 02:28:16 -05:00
kcbanner
4a330ab811 target: use 16 byte alignment for 128-bit types on x86 and ofmt .c 2023-01-23 13:48:37 -05:00
Maciej 'vesim' Kuliński
2b9478ce12 Sema: implement AVR address spaces
Co-authored-by: Veikka Tuominen <git@vexu.eu>
2023-01-04 01:26:50 +02:00
Michael Dusan
46c3b09165
std.Target: bump semver max for BSDs
- freebsd, netbsd, openbsd, dragonfly
2023-01-02 19:18:33 -05:00
zooster
728cc73819 std.Target.ObjectFormat: specify dxcontainer file ext 2022-12-26 18:03:27 -05:00
Robin Voetter
074ba69ba6
spirv: assembler
spirv: introduce SpvModule.Fn to generate function code into

spirv: assembler error message setup

spirv: runtime spec info

spirv: inline assembly tokenizer

spirv: inline assembly lhs result/opcode parsing

spirv: forgot to fmt

spirv: tokenize opcodes and assigned result-ids

spirv: operand parsing setup

spirv: assembler string literals

spirv: assembler integer literals

spirv: assembler value enums

spirv: assembler bit masks

spirv: update assembler to new asm air format

spirv: target 1.5 for now

Current vulkan sdk version (1.3.204) ships spirv tools targetting 1.5,
and so these do not work with binaries targetting 1.6 yet. In the
future, this version number should be decided by the target.

spirv: store operands in flat arraylist.

Instead of having dedicated Operand variants for variadic operands,
just flatten them and store them in the normal inst.operands list.
This is a little simpler, but is not easily decodable in the operand
data representation.

spirv: parse variadic assembly operands

spirv: improve assembler result-id tokenization

spirv: begin instruction processing

spirv: only remove decl if it was actually allocated

spirv: work around weird miscompilation

Seems like there are problems with switch in anonymous struct literals.

spirv: begin resolving some types in assembler

spirv: improve instruction processing

spirv: rename some types + process OpTypeInt

spirv: process OpTypeVector

spirv: process OpTypeMatrix and OpTypeSampler

spirv: add opcode class to spec, remove @exclude'd instructions

spirv: process more type instructions

spirv: OpTypeFunction

spirv: OpTypeOpaque

spirv: parse LiteralContextDependentNumber operands

spirv: emit assembly instruction into right section

spirv: parse OpPhi parameters

spirv: inline assembly inputs

spirv: also copy air types

spirv: inline assembly outputs

spirv: spir-v address spaces

spirv: basic vector constants/types and shuffle

spirv: assembler OpTypeImage

spirv: some stuff

spirv: remove spirv address spaces for now
2022-11-23 19:17:58 +01:00
Nick Cernis
8a5818535b
Make invalidFmtError public and use in place of compileErrors for bad format strings (#13526)
* Export invalidFmtErr

To allow consistent use of "invalid format string" compile error
response for badly formatted format strings.

See https://github.com/ziglang/zig/pull/13489#issuecomment-1311759340.

* Replace format compile errors with invalidFmtErr

- Provides more consistent compile errors.
- Gives user info about the type of the badly formated value.

* Rename invalidFmtErr as invalidFmtError

For consistency. Zig seems to use “Error” more often than “Err”.

* std: add invalid format string checks to remaining custom formatters

* pass reference-trace to comp when building build file; fix checkobjectstep
2022-11-12 21:03:24 +02:00
Jay Petacat
694d8831c3 Revert "x86" CPU model (not arch) back to "i386"
PR #13101 recently renamed the "i386" architecture to "x86", and it
seems the specific CPU model got swept up in that. "x86" is an umbrella
term that describes a family of CPUs, and the "i386" is the oldest
supported model under that umbrella.
2022-11-06 13:39:03 +01:00
Ali Chraghi
f5f1f8c666 all: rename i386 to x86 2022-11-04 00:09:27 +03:30
Jacob Young
93d60d0de7 std: avoid vector usage with the C backend
Vectors are not yet implemented in the C backend, so no reason to
prevent code using the standard library from compiling in the meantime.
2022-11-01 20:38:37 -04:00
Andrew Kelley
1d1c7ae5de
Merge pull request #13257 from topolarity/ctype-fixes
stage 2: Update `CType` size/alignment
2022-10-27 21:15:22 -04:00
Jakub Konka
2d03f38988 darwin: bump minimum supported version to 11.7.1
Drop Catalina support.
2022-10-25 20:31:48 +02:00
Jakub Konka
98285b17b3 darwin: bump max macOS version to 13.0 2022-10-25 20:31:31 +02:00
Cody Tapscott
f0e66ac4d0 std.Target: Remove longDoubleIs
This function is redundant with CType.sizeInBits(), and until the
previous commit they disagreed about the correct long double type
for several targets. Although they're all synced up now, it's much
simpler just to have a single source of truth.
2022-10-21 19:20:58 -07:00
Cody Tapscott
ddbdb83c86 stage 2: Update C types' size/alignment
These updates were made by testing against the `sizeof/_Alignof` reported
by Clang for all supported arch-OS-ABI combinations and correcting any
discrepancies.

This is bound to have a few errors (the recent long double fix for i386
Android is one example), but Clang is certainly not a bad place to start,
especially for our most popular targets.
2022-10-21 19:11:47 -07:00
Andrew Kelley
5b9c8d1d6f add m68k target CPU features 2022-10-20 09:21:06 -07:00
Guillaume Wenzek
aad983cf40 sanitize qualified name for nvptx backend 2022-10-15 10:39:19 -07:00
Andrew Kelley
66d6183001 Merge branch 'amdgpu-improvements' of https://github.com/Snektron/zig into Snektron-amdgpu-improvements 2022-10-15 10:36:10 -07:00
Andrew Kelley
b4e3424594
Merge pull request #13100 from topolarity/powerpc64le
stage2: Fix softfloat support for PPC64(LE)
2022-10-15 10:05:00 -04:00
Evan Haas
e4e1c21e1f i386 ABI: Fix some sizes and alignments
This makes the following changes for i386:

long long and unsigned long long have 4 byte alignment on non-Windows

f64 (double) has 4-byte alignment on non-Windows

long double is 80 bits and has 4 byte alignment on mingw

long double on android is 64 bits, not 80: https://www.uclibc.org/docs/psABI-i386.pdf

Fixes #12453
Fixes #12987
2022-10-14 15:22:00 -04:00
Cody Tapscott
37c6fcafa2 stage2 LLVM: Correct long double for WASM
Also, f16 is not supported on this backend.
2022-10-13 12:53:20 -07:00
Robin Voetter
9ff60e356e
typo 2022-10-12 20:38:43 +02:00
Robin Voetter
9f14681473
stage2: check address space cast validity 2022-10-12 20:36:14 +02:00
Andrew Kelley
de7270028d Merge remote-tracking branch 'origin/master' into llvm15 2022-08-29 14:10:59 -07:00
Andrew Kelley
cee82c7ce4 improved ABI alignment/size for >= 128-bit integers
* riscv64: adjust alignment and size of 128-bit integers.
 * take ofmt=c into account for ABI alignment of 128-bit integers and
   structs.
 * Type: make packed struct support intInfo
 * fix f80 alignment for i386-windows-msvc
2022-08-18 20:34:36 -07:00
Andrew Kelley
b975f7a56f std.Target gains ObjectFormat field 2022-08-18 18:58:28 -07:00
Andrew Kelley
6e313eb110 stage2: agree with LLVM that @alignOf(u128) is 8
on x86_64 and similar targets.
2022-08-18 17:11:32 -07:00
Veikka Tuominen
bd21f499dc Type: adjust C type sizes 2022-08-06 14:42:05 -07:00
Andrew Kelley
70d3912390 update Target, CPU, OS, ABI, etc. to LLVM 15 2022-07-31 18:10:28 -07:00
Meghan Denny
b5861193e0 std: rename std.Target.systemz to .s390x 2022-07-28 23:22:44 -07:00
Andrew Kelley
d55d98919d update CPU features to LLVM 14
Notable changes:

`_i386`, `_i486`, and `_i686` are renamed to `i386`, `i486`,
and `i686` respectively. `std.zig.fmtId` is enhanced to support
formatting `i386` as `@"i386"`.

Some CPU features which are actually CPU models have been
properly flattened, such as `apple_a12`, `apple_a13`, `apple_a7`,
`cortex_a78c`, `exynos_m4`, `neoverse_e1`, `neoverse_n1`,
`neoverse_n2`, `neoverse_v1`.

Some CPU features have been added and some have been removed, following
LLVM's lead.

CSky CPU features support is added.
2022-07-01 21:35:19 -07:00
Andrew Kelley
c89dd15e1b Merge remote-tracking branch 'origin/master' into llvm14 2022-07-01 15:52:54 -07:00
Jakub Konka
cbefd354a6 Bump support macOS versions; clean up allocs in llvm.targetTriple 2022-05-22 22:31:41 +02:00
Jakub Konka
5b813f1a2a Set macOS/iPhoneOS/tvOS/watchOS ABI to none (unspecified) by default
Prior to this change we would assume the ABI for Apple targets to
be GNU which could result in subtle errors in LLVM emitting calls
to non-existent system libc provided functions such as `_sincosf`
which is a GNU extension and as such is not provided by macOS for example.
This would result in linker errors where the linker would not be
able to find the said symbol in `libSystem.tbd`.

With this change, we now correctly identify macOS (and other Apple
platforms) as having ABI `unknown` which translates to unspecified
in LLVM under-the-hood:

```
// main.ll
target triple = "aarch64-unknown-macos-unknown"
```

Note however that we never suffix the target OS with target version
such as `macos11` or `macos12` which means we fail to instruct LLVM
of potential optimisations provided by the OS such as the availability
of function `___sincosf_stret`. I suggest we investigate that in a
follow-up commit.
2022-05-22 17:45:02 +02:00
Koakuma
fb0692334e target: Rename sparcv9 -> sparc64
Rename all references of sparcv9 to sparc64, to make Zig align more with
other projects. Also, added new function to convert glibc arch name to Zig
arch name, since it refers to the architecture as sparcv9.

This is based on the suggestion by @kubkon in PR 11847.
(https://github.com/ziglang/zig/pull/11487#pullrequestreview-963761757)
2022-05-13 16:43:59 -04:00
Andrew Kelley
0bebb688fb stage2: change max int align from 8 to 16 for more ISAs
These targets now have a similar disagreement with LLVM about the
alignment of 128-bit integers as x86_64:
 * riscv64
 * powerpc64
 * powerpc64le
 * mips64
 * mips64el
 * sparcv9

See #2987
2022-05-04 19:11:02 -07:00
Andrew Kelley
f21c11a7f7 stage2: change x86_64 max int alignment from 8 to 16
For x86_64, LLVMABIAlignmentOfType(i128) reports 8. However I think 16
is a better number for two reasons:
1. Better machine code when loading into SIMD register.
2. The C ABI wants 16 for extern structs.
2022-05-04 17:34:17 -07:00
Andrew Kelley
259f784241 stage2: improve @sizeOf and @alignOf integers
Prior to this commit, the logic for ABI size and ABI alignment for
integers was naive and incorrect. This results in wasted hardware as
well as undefined behavior in the LLVM backend when we memset an
incorrect number of bytes to 0xaa due to disagreeing with LLVM about the
ABI size of integers.

This commit introduces a "max int align" value which is different per
Target. This value is used to derive the ABI size and alignment of all
integers.

This commit makes an interesting change from stage1, which treats
128-bit integers as 16-bytes aligned for x86_64-linux. stage1 is
incorrect. The maximum integer alignment on this system is only 8 bytes.
This change breaks the behavior test called "128-bit cmpxchg" because on
that target, 128-bit cmpxchg does require a 16-bytes aligned pointer to
a 128 bit integer. However, this alignment property does not belong on
*all* 128 bit integers - only on the pointer type in the `@cmpxchg`
builtin function prototype. The user can then use an alignment override
annotation on a 128-bit integer variable or struct field to obtain such
a pointer.
2022-05-04 17:34:16 -07:00
r00ster91
bb55276f06 Avoid some unnecessary underscores in constant names 2022-05-02 15:29:04 -04:00
Veikka Tuominen
6d48600ea0
Merge pull request #10717 from gh-fork-dump/seccomp-bits
Add Seccomp bits for linux
2022-04-28 18:54:09 +03:00
Jakub Konka
897df18573 stage2: fix @mulAdd on aarch64 Darwin
According to Apple docs, the long double type is a double precision
IEEE754 binary floating-point type, which makes it identical to the
double type. This behavior contrasts to the standard specification,
in which a long double is a quad-precision, IEEE754 binary,
floating-point type.

Thus, we need to take this into account when using the compiler
intrinsics so that we select the correct function version for
FloatMulAdd.
2022-04-16 12:23:47 +02:00
Meghan
b73cf97c93
replace other uses of std.meta.Vector with @Vector (#11346) 2022-03-30 14:12:14 -04:00
Andrew Kelley
71b8760d3b stage2: rework @mulAdd
* mul_add AIR instruction: use `pl_op` instead of `ty_pl`. The type is
   always the same as the operand; no need to waste bytes redundantly
   storing the type.
 * AstGen: use coerced_ty for all the operands except for one which we
   use to communicate the type.
 * Sema: use the correct source location for requireRuntimeBlock in
   handling of `@mulAdd`.
 * native backends: handle liveness even for the functions that are
   TODO.
 * C backend: implement `@mulAdd`. It lowers to libc calls.
 * LLVM backend: make `@mulAdd` handle all float types.
   - improved fptrunc and fpext to handle f80 with compiler-rt calls.
 * Value.mulAdd: handle all float types and use the `@mulAdd` builtin.
 * behavior tests: revert the changes to testing `@mulAdd`. These
   changes broke the test coverage, making it only tested at
   compile-time.

Improved f80 support:
 * std.math.fma handles f80
 * move fma functions from freestanding libc to compiler-rt
   - add __fmax and fmal
   - make __fmax and fmaq only exported when they don't alias fmal.
   - make their linkage weak just like the rest of compiler-rt symbols.
 * removed `longDoubleIsF128` and replaced it with `longDoubleIs` which
   takes a type as a parameter. The implementation is now more accurate
   and handles more targets. Similarly, in stage2 the function
   CTypes.sizeInBits is more accurate for long double for more targets.
2022-03-06 16:11:39 -07:00
gwenzek
0e1afb4d98
stage2: add support for Nvptx target
sample command:

/home/guw/github/zig/stage2/bin/zig build-obj cuda_kernel.zig -target nvptx64-cuda -O ReleaseSafe
this will create a kernel.ptx

expose PtxKernel call convention from LLVM
kernels are `export fn f() callconv(.PtxKernel)`
2022-02-05 16:33:00 +02:00
Andrew Kelley
5466e87fce update C API bindings to LLVM 14
* zig_clang is fully updated
 * zig_llvm is fully updated

Some initial work on codegen.cpp is in place for upgrading to LLVM's
new opaque pointers. However there is much more to be done.

A few of zig llvm bindings for deprecated functions have been updated;
more need to be updated.
2022-02-03 16:49:24 -07:00
Andrew Kelley
75bbc74d56 a small crusade against std.meta.declarations 2022-01-31 22:25:49 -07:00
ominitay
8ca9452a82 Remove deprecation warnings and enable test
Also fixes previously broken code uncovered by this
2022-01-29 15:49:00 +02:00