7246 Commits

Author SHA1 Message Date
joachimschmidt557
8a0e86cd5c
stage2 ARM: implement load for types with size 8 (e.g. slices) 2021-12-26 17:05:08 +01:00
joachimschmidt557
15f0f9240d
stage2 codegen: Implement generateSymbol for undefined values 2021-12-26 16:40:51 +01:00
Andrew Kelley
6b8e33d14c stage2: LLVM: fix lowering of packed structs
* ensure enough capacity when building the LLVM type and value.
 * add explicit padding field and populate it to ensure proper
   alignment.
2021-12-24 02:37:54 -07:00
Andrew Kelley
5b171f446f stage2: initial implementation of packed structs
Layout algorithm: all `align(0)` fields are squished together as if they
were a single integer with a number of bits equal to `@bitSizeOf` each
field added together. Then the natural ABI alignment of that integer is
used for that pseudo-field.
2021-12-23 23:57:02 -07:00
Andrew Kelley
0049c7180f
Merge pull request #10394 from ziglang/stage2-x86_64-mir-intel-syntax
stage2: rewrite MIR -> Isel layer for x86_64
2021-12-23 16:39:51 -08:00
Andrew Kelley
4c11986650
MIR: remove unnecessary TODO comment
it wouldn't save any bytes in the MIR, and we can just check the range of the value when lowering the MIR to machine code.
2021-12-23 16:39:28 -08:00
Jakub Konka
35fe088e0e stage2: add lowering of RMI encoding
Example includes imul with 3 operands such as imul r64, r/m64, imm32.
2021-12-23 21:14:14 +01:00
Jakub Konka
dba5df64ea stage2: use lowerToRmEnc to lower two-operand imul
Fix mismatched register sizes in codegen.
2021-12-23 20:51:48 +01:00
Jakub Konka
c50bb2b80f stage2: lower jcc and setcc conditional jump/set instructions 2021-12-23 20:29:34 +01:00
Jakub Konka
8c664d3f6a stage2: support multibyte opcodes and refactor 1byte opcode changes 2021-12-23 18:49:40 +01:00
Jakub Konka
d23a1487bd stage2: add lowering of ZO encoding
ZO (probably) stands for zero operands encoding which is effectively
only the opcode.
2021-12-23 18:49:40 +01:00
Jakub Konka
a70b4068c6 stage2: add lowering to I encoding
Examples include push imm32.
2021-12-23 10:22:23 +01:00
Jakub Konka
b657956c44 stage2: add lowering to O encoding
Example includes push/pop register.
2021-12-23 09:47:38 +01:00
Andrew Kelley
cc937369fb stage2: Type.hasCodeGenBits asserts structs and unions have fields
Previously, this function would return an incorrect result for structs
and unions which did not have their fields resolved yet.

This required introducing more logic in Sema to resolve types before
doing certain things such as creating an anonmyous Decl and emitting
function call AIR.

As a result a couple more struct tests pass.

Oh, and I implemented the language change to make sizeOf for pointers
always return pointer size bytes even if the element type is 0 bits.
2021-12-22 20:29:26 -07:00
Luuk de Gram
e061d75cdf wasm-linker: Implement symbol names emitting
The linker will now emit names for all function, global and data segment symbols.
This increases the ability to debug wasm modules tremendously as tools like wasm2wat
can use this information to generate named functions, globals etc, rather than placeholders such as $f1.
2021-12-23 01:47:45 +01:00
Jakub Konka
603f826779 stage2: migrate push/pop r/m64 to new lowering mechanism 2021-12-23 01:30:25 +01:00
Jakub Konka
9078cb0197 stage2: add lowering of M encoding
Examples include jmp / call near with memory or register operand
like `jmp [rax]`, or even RIP-relative `call [rip + 0x10]`.
2021-12-23 01:22:07 +01:00
Jakub Konka
1167e248ef stage2: add lowering of D encoding
Example of such encoding includes a near/far call and jmp instructions.
2021-12-23 00:43:38 +01:00
Jakub Konka
362eccf539 stage2: handle RIP relative addressing in MI, RM and MR 2021-12-22 23:07:46 +01:00
Jakub Konka
b40e5adf54 stage2: add lowering for FD/TD encodings 2021-12-22 22:36:56 +01:00
Jakub Konka
b9a6f81d1a stage2: add lowering fn for OI encoding
Implement movabs using OI generic encoding.
2021-12-22 19:01:43 +01:00
Jakub Konka
2b5de9403d stage2: create generic lowering fns for MI, RM, and MR encodings
This way I am hopeful they can be reused for every MIR lowering
function which follows a given encoding. Currently, support MI,
RM and MR encodings without SIB scaling.
2021-12-22 18:10:52 +01:00
Andrew Kelley
6fdf7ce0af Sema: simplify coercion logic
Instead of a separate function, `coerceNum` for handling comptime-known
number coercion, outside of the main switch, the `coerce` function now
has a single big switch statement that decides the control flow based on
the zig type tag.
2021-12-21 22:35:24 -07:00
Andrew Kelley
5d6380b38d
Merge pull request #10384 from joachimschmidt557/stage2-arm-optionals
stage2 ARM: basic implementation of optionals and error unions
2021-12-21 21:06:08 -08:00
Andrew Kelley
88be5bd81d Sema: fix empty struct init
* Extract common logic between `zirStructInitEmpty` and
   `zirStructInit`.
 * `resolveTypeFields` additionally sets status to `have_layout` if the
   total number of fields is 0.
2021-12-21 20:34:27 -07:00
Andrew Kelley
06d751dbb3 link/wasm: fix regression of wrong assertion
Fixes typo introduced in 2cbeb85a96af25f2718a604aa2bec4f76dd85018.
2021-12-21 18:43:19 -07:00
Andrew Kelley
2cbeb85a96 stage2: error check for mixing --import-table and --export-table
is moved from the linker to the frontend. This is a follow-up from
4cb2f11693b1bf13770b8ad6a8b8a1e37101a516.
2021-12-21 18:21:42 -07:00
joachimschmidt557
c55f58d8bb
stage2 ARM: implement is_err and is_non_err for simple error unions 2021-12-21 23:13:30 +01:00
joachimschmidt557
edcebe7013
stage2 ARM: implement is_null and is_non_null for ptr-like optionals 2021-12-21 23:13:30 +01:00
Andrew Kelley
8b6ea9ffe7 C backend: implement ret_addr 2021-12-21 14:32:02 -07:00
Luuk de Gram
4cb2f11693 wasm-linker: Implement the --export-table and --import-table flags.
This implements the flags for both the linker frontend as well as the self-hosted linker.

Closes #5790
2021-12-21 12:38:50 -08:00
Ersikan
e15a267668 elf: Put constant data in the .rodata section
Allocate a new program header and a new section to accomodate the read-only data
section ".rodata".

Separate TextBlock into multiple TextBlockList, to separate decl in different
sections.

If a Decl is not a function, it is added to the .rodata section.
2021-12-21 11:33:12 -08:00
joachimschmidt557
44061cd760 stage2 ARM: Refactor airStore 2021-12-21 11:30:56 -08:00
Robin Voetter
e106e18d96 stage2: @shlWithOverflow 2021-12-21 01:47:27 +01:00
Robin Voetter
964dbeb826 stage2: @subWithOverflow 2021-12-21 01:41:51 +01:00
Robin Voetter
58d67a6718 stage2: make anyopaque sized
While this is technically incorrect, proper handling of anyopaque, as well
as regular opaque, is probably best left until pointers to zero-sized types
having no bits is abolished.
2021-12-21 01:41:51 +01:00
Robin Voetter
c47ed0c912 stage2: @mulWithOverflow 2021-12-21 01:41:51 +01:00
Robin Voetter
ddd2ef822f stage2: @returnAddress() 2021-12-21 01:41:51 +01:00
Robin Voetter
2f7e98c129 stage2: also write addrspace to pointer typeinfo 2021-12-21 01:41:51 +01:00
Robin Voetter
f3d635b668 stage2: @addWithOverflow 2021-12-21 01:41:51 +01:00
Robin Voetter
138f85bf25 stage2: only create inferred error sets for inferred error set functions 2021-12-21 01:41:50 +01:00
Robin Voetter
16bddecff9 stage2: allow @ptrToInt on anything that is a pointer at runtime
This in particular allows @ptrToInt on pointer-like optionals.
2021-12-21 01:41:50 +01:00
Robin Voetter
d5621504b0 stage2: save and restore parameters when resolving inline bodies
This caused zirParam instructions of parent blocks to be present in
inline analyzed blocks, and so function prototypes declared in the
inline blocks would also gain and add to the parameters in the
parent block.

Only block and block_inline are affected in this commit, as prototypes
and declarations are always generated in block_inline. This might need
to be resolved in a more general way at some point.
2021-12-21 01:41:50 +01:00
Robin Voetter
e18c3f3109 stage2: wrap function prototypes in an inline block.
Previously, function parameter instructions for function prototypes would be
generated in the parent block. This caused issues in blocks where multiple
prototypes would be generated in, such as the block for struct fields for
example. This change introduces an inline block around every prototype such
that all parameters for a prototype are confined to a unique block.
2021-12-21 01:41:50 +01:00
Robin Voetter
993197cd86 stage2: merged error sets in wrapErrorUnion 2021-12-21 01:41:50 +01:00
Robin Voetter
9d6c45f697 stage2: inferred error set coercion 2021-12-21 01:41:50 +01:00
Robin Voetter
a2958a4ede stage2: allow multiple inferred error sets per Fn
This allows the inferred error set of comptime and inline invocations to be
resolved separately from the inferred error set of the runtime version or other
comptime/inline invocations.
2021-12-21 01:41:50 +01:00
Robin Voetter
b2343e63bd stage2: move inferred error set state into func 2021-12-21 01:41:50 +01:00
Robin Voetter
cd733ceb85 stage2: replace ErrorSet and ErrorSetMerged arrays with hash maps 2021-12-21 01:41:50 +01:00
Jakub Konka
5156ccd552 stage2: merge MOV back with arith instructions
* turns out MOV and other arithmetic instructions such as ADD can
  naturally share the same lowering codepath (for the same variants)
* there are variants that are specific to ADD, or MOV which will be
  implemented as standalone MIR tags
* tweak Isel tests to generate corresponding test cases for all
  arithmetic instructions in comptime
2021-12-20 23:29:41 +01:00