Andrew Kelley
e7f128c205
Merge pull request #14782 from r00ster91/trap
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add `@trap` builtin
2023-03-04 16:20:31 -05:00
r00ster91
4eb3f50fcf
Wasm @breakpoint: emit unreachable
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This should improve the developer debugging experience.
2023-03-04 12:08:23 +01:00
r00ster91
65368683ad
add @trap builtin
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This introduces a new builtin function that compiles down to something that results in an illegal instruction exception/interrupt.
It can be used to exit a program abnormally.
This implements the builtin for all backends.
2023-03-04 12:08:19 +01:00
Jakub Konka
dc709fbf48
codegen: rename GenerateSymbolError to CodeGenError
2023-03-03 18:56:57 +01:00
Jakub Konka
f6eeb6c8ce
sparc64: use common implementation of genTypedValue
2023-03-03 18:53:30 +01:00
Jakub Konka
5b3ea49806
riscv64: use common implementation of genTypedValue
2023-03-03 18:53:13 +01:00
Jakub Konka
0d2c25ca9d
aarch64: use common implementation of genTypedValue
2023-03-03 18:46:08 +01:00
Jakub Konka
1024332adc
arm: use common implementation of genTypedValue helper
2023-03-03 18:24:58 +01:00
Jakub Konka
c746cbc686
codegen: move gen logic for typed values, consts and decl ref to common codegen
2023-03-03 18:06:25 +01:00
Jacob Young
6bed45b873
codegen: fix test failures
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Various backend were mismatching arg instructions and function args.
2023-02-27 16:30:15 -05:00
Isaac Freund
05da5b32a8
Sema: implement @fieldParentPtr for unions
2023-02-21 15:57:13 +02:00
Jakub Konka
dc1f50e505
Merge pull request #14685 from ziglang/bitcast-fixes
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Bitcast fixes for self-hosted native backends
2023-02-20 23:01:21 +01:00
Jakub Konka
0aee40bd13
riscv64+sparc64: alloc new mcv in bitcast if cannot reuse operand
2023-02-20 12:19:40 +01:00
Jakub Konka
528c43233f
arm: alloc new mcv in bitcast if cannot reuse operand
2023-02-20 12:13:14 +01:00
Jakub Konka
59a9373c71
aarch64: alloc new mcv in bitcast if cannot reuse operand
2023-02-20 10:52:34 +01:00
Jakub Konka
a7de8dc2dd
x86: alloc new mcv in bitcast if cannot reuse operand
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Implement missing pointees when ptr is in register.
2023-02-20 10:52:26 +01:00
Veikka Tuominen
f10950526e
implement writeToMemory/readFromMemory for pointers
2023-02-19 13:54:52 -05:00
Andrew Kelley
aeaef8c0ff
update std lib and compiler sources to new for loop syntax
2023-02-18 19:17:21 -07:00
Luuk de Gram
c9b957c937
link: remove FnData and make it self-owned
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This finishes the work started in #14502 where atoms are owned by the
linker themselves. This now makes debug atoms fully owned by dwarf,
and no information is left stored on the decl.
2023-02-03 22:55:46 +01:00
Jakub Konka
304420b99c
Merge pull request #14502 from ziglang/link-owned-atoms
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link: move ownership of linker atom from frontend to the linkers
2023-02-02 01:39:01 +01:00
Jakub Konka
beb20d29db
link: remove union types which are now internal to backends
2023-02-01 19:32:54 +01:00
Luuk de Gram
46f54b23ae
link: make Wasm atoms fully owned by the linker
2023-02-01 19:10:56 +01:00
Jakub Konka
5de2aae63c
link: decouple DI atoms from linker atoms, and manage them in Dwarf linker
2023-02-01 15:03:55 +01:00
Jakub Konka
b3277c8936
link: make Plan9 atoms fully owned by the linker
2023-02-01 11:12:53 +01:00
Jakub Konka
c430e9afa7
link: make Coff atoms fully owned by the linker
2023-01-31 20:27:17 +01:00
Jakub Konka
4404c4d200
link: make Elf atoms fully owned by the linker
2023-01-31 17:54:12 +01:00
Techatrix
47ff57ed7d
wasm: apply request change
2023-01-31 17:01:56 +01:00
Techatrix
1f64432196
wasm: correctly handle optional slices
2023-01-31 00:59:18 +01:00
Jakub Konka
d42a931051
link: make MachO atoms fully owned by the linker
2023-01-31 00:43:25 +01:00
joachimschmidt557
090186a0c2
stage2 AArch64: move copy-register-arg-to-stack code to fn prologue
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This enhances the debugging experience as upon encountering a
breakpoint in a function, all arguments passed as registers have
already been moved to the stack, ready to be inspected by the
debugger.
2023-01-29 20:00:53 +01:00
Luuk de Gram
b25efb86e1
wasm: migrate to new non-allocateDeclIndexes API
2023-01-27 19:24:15 +01:00
Jakub Konka
cc1d7a0e31
coff: migrate to new non-allocateDeclIndexes API
2023-01-26 14:29:14 +01:00
Jakub Konka
e1b9800ffa
elf: migrate to new non-allocateDeclIndexes API
2023-01-26 14:29:14 +01:00
Jakub Konka
041bc71bc8
self-hosted: clean up calling logic for x86_64 and aarch64 across linkers
2023-01-26 14:29:14 +01:00
Jakub Konka
4d804c1b23
macho: completely remove allocateDeclIndexes in favor of linker tracking
2023-01-26 14:29:14 +01:00
Jakub Konka
a95d58caf2
self-hosted: rename codegen Result.appended to Result.ok
2023-01-25 10:28:18 +01:00
Jakub Konka
4983da40d0
self-hosted: remove unused externally_managed prong for Decls code
2023-01-25 10:10:50 +01:00
joachimschmidt557
c0284e242f
stage2 ARM: add basic debug info for locals
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Also disables one behavior test which was failing
2023-01-22 12:00:04 +01:00
Veikka Tuominen
0013042cbd
llvm: correctly handle C ABI structs with f32/f64 alignment differences
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Closes #13830
2023-01-14 16:26:50 +02:00
Veikka Tuominen
5572c67e73
add C ABI tests for exotic float types
2023-01-14 16:26:50 +02:00
joachimschmidt557
09122650ba
stage2 AArch64: bump up alignment of stack items fitting in regs
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This enables us to use more efficient loading and storing for these
small stack items
2023-01-03 19:56:09 +01:00
Veikka Tuominen
af197d4954
Merge pull request #14130 from Vexu/debug-info
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Debug info fixes
2022-12-31 11:47:56 +02:00
Manlio Perillo
2419061246
x86_64: remove extra whitespace
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Remove extra whitespace at the end of a line in Emit.zig, in regions
where zig fmt is off.
2022-12-30 15:01:19 -05:00
Veikka Tuominen
4e64373fc0
fix generic function arg debug info referencing wrong parameter
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Closes #14123
2022-12-30 17:00:50 +02:00
joachimschmidt557
1caf56c5fb
stage2 AArch64: implement errUnion{Err,Payload} for registers
2022-12-29 11:12:08 +01:00
joachimschmidt557
485082064a
stage2 AArch64: implement field_parent_ptr
2022-12-27 21:26:18 +08:00
joachimschmidt557
d6e6162081
stage2 AArch64: unify callee-preserved regs on all targets
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also enables many passing behavior tests
2022-12-27 21:17:52 +08:00
Luuk de Gram
0d66112643
wasm: refactor extended instructions
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The extended instructions starting with opcode `0xFC` are refactored
to make the work the same as the SIMD instructions. This means a
`Mir` instruction no longer contains a field 'secondary'. Instead,
we use the `payload` field to store the index into the extra list
which contains the extended opcode value. In case of instructions
such as 'memory.fill' which also have an immediate value, such
values will also be stored in the extra list right after the
instruction itself. This makes each `Mir` instruction smaller.
2022-12-21 17:02:53 +01:00
Veikka Tuominen
9f23702c21
llvm: fix C ABI for <=256 bit vectors
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Closes #13918
2022-12-20 18:34:33 +02:00
Andrew Kelley
aca9c74e80
Merge pull request #13914 from Vexu/variadic
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implement defining C variadic functions
2022-12-18 16:24:13 -05:00
