222 Commits

Author SHA1 Message Date
Ryan Liptak
59f5053bed Update all ensureCapacity calls to the relevant non-deprecated version 2021-09-19 13:52:56 +02:00
Andrew Kelley
b67d1810be stage2: implement @atomicRmw and @atomicLoad
* langref: add some more "see also" links for atomics
 * Add the following AIR instructions
   - atomic_load
   - atomic_store_unordered
   - atomic_store_monotonic
   - atomic_store_release
   - atomic_store_seq_cst
   - atomic_rmw
 * Implement those AIR instructions in LLVM and C backends.
 * AstGen: make the `ty` result locations for `@atomicRmw`, `@atomicLoad`,
   and `@atomicStore` be `coerced_ty` to avoid unnecessary ZIR
   instructions when Sema will be doing the coercions redundantly.
 * Sema for `@atomicLoad` and `@atomicRmw` is done, however Sema for
   `@atomicStore` is not yet implemented.
   - comptime eval for `@atomicRmw` is not yet implemented.
 * Sema: flesh out `coerceInMemoryAllowed` a little bit more. It can now
   handle pointers.
2021-09-15 19:00:35 -07:00
Andrew Kelley
19691c0b17 stage2: implement @fence 2021-09-15 12:37:32 -07:00
Jakub Konka
25416d8121 macho: when adding extern fn, check if already resolved
This way, we will generate valid relocation info in the codegen.
2021-09-15 16:51:56 +02:00
Andrew Kelley
0395b35cee stage2: implement cmpxchg and improve comptime eval
* Implement Sema for `@cmpxchgWeak` and `@cmpxchgStrong`. Both runtime
   and comptime codepaths are implement.
 * Implement Codegen for LLVM backend and C backend.
 * Add LazySrcLoc.node_offset_builtin_call_argX 3...5
 * Sema: rework comptime control flow.
   - `error.ComptimeReturn` is used to signal that a comptime function
     call has returned a result (stored in the Inlining struct).
     `analyzeCall` notices this and handles the result.
   - The ZIR instructions `break_inline`, `block_inline`,
     `condbr_inline` are now redundant and can be deleted. `break`,
     `block`, and `condbr` function equivalently inside a comptime scope.
   - The ZIR instructions `loop` and `repeat` also are modified to
     directly perform comptime control flow inside a comptime scope,
     skipping an unnecessary mechanism for analysis of runtime code.
     This makes Zig perform closer to an interpreter when evaluating
     comptime code.
 * Sema: zirRetErrValue looks at Sema.ret_fn_ty rather than sema.func
   for adding to the inferred error set. This fixes a bug for
    inlined/comptime function calls.
 * Implement ZIR printing for cmpxchg.
 * stage1: make cmpxchg respect --single-threaded
   - Our LLVM C++ API wrapper failed to expose this boolean flag before.
 * Fix AIR printing for struct fields showing incorrect liveness data.
2021-09-14 21:58:22 -07:00
Jakub Konka
85f065a511
Merge pull request #9676 from ziglang/zld-incr
MachO: merges stage1 with self-hosted codepath
2021-09-14 14:20:11 +02:00
Andrew Kelley
97d69e3352 stage2: add array_to_slice AIR instruction 2021-09-13 21:37:11 -07:00
Jakub Konka
a38b636045 Merge remote-tracking branch 'origin/master' into zld-incr 2021-09-13 23:40:38 +02:00
Andrew Kelley
332eafeb7f stage2: first pass at implementing usingnamespace
Ran into a design flaw here which will need to get solved by having
AstGen annotate ZIR with which instructions are closed over.
2021-09-01 17:54:06 -07:00
Andrew Kelley
3b9ec4e4df
Merge pull request #9655 from nektro/stage2-rem
stage2: implement runtime `%` and `@rem`
2021-08-31 21:59:48 -04:00
joachimschmidt557
4334dbb9a5 stage2 codegen: Remove use of usingnamespace 2021-08-30 13:40:03 -04:00
Meghan Denny
e878a6633f stage2: implement runtime % and @rem 2021-08-30 00:31:40 -07:00
Jakub Konka
29df0ca39d Merge remote-tracking branch 'origin/master' into zld-incr 2021-08-26 14:35:34 +02:00
Jakub Konka
ee786e5c3c macho: add GOT entries as actual atoms 2021-08-25 17:23:30 +02:00
Jacob G-W
4ac37eb484 stage2 Air: add struct_field_ptr_index_{0..3}
Since these are very common, it will save memory.
2021-08-21 23:52:55 -04:00
joachimschmidt557
5806c386eb stage2 codegen: re-allocate result register in finishAir
In some cases (such as bitcast), an operand may be the same MCValue as
the result. If that operand died and was a register, it was freed by
processDeath. We have to "re-allocate" the register.
2021-08-20 19:06:30 -04:00
joachimschmidt557
e48d7bbb99 stage2 ARM: Implement loading from memory 2021-08-20 19:05:50 -04:00
Andrew Kelley
a2438357e1
Merge pull request #9597 from joachimschmidt557/stage2-arm-bitshift
stage2 ARM: implement bitshifts
2021-08-20 19:05:05 -04:00
Andrew Kelley
0cd361219c stage2: field type expressions support referencing locals
The big change in this commit is making `semaDecl` resolve the fields if
the Decl ends up being a struct or union. It needs to do this while
the `Sema` is still in scope, because it will have the resolved AIR
instructions that the field type expressions possibly reference. We do
this after the decl is populated and set to `complete` so that a `Decl`
may reference itself.

Everything else is fixes and improvements to make the test suite pass
again after making this change.

 * New AIR instruction: `ptr_elem_ptr`
   - Implemented for LLVM backend
 * New Type tag: `type_info` which represents `std.builtin.TypeInfo`. It
   is used by AstGen for the operand type of `@Type`.
 * ZIR instruction `set_float_mode` uses `coerced_ty` to avoid
   superfluous `as` instruction on operand.
 * ZIR instruction `Type` uses `coerced_ty` to properly handle result
   location type of operand.

 * Fix two instances of `enum_nonexhaustive` Value Tag not handled
   properly - it should generally be handled the same as `enum_full`.
 * Fix struct and union field resolution not copying Type and Value
   objects into its Decl arena.
 * Fix enum tag value resolution discarding the ZIR=>AIR instruction map
   for the child Sema, when they still needed to be accessed.
 * Fix `zirResolveInferredAlloc` use-after-free in the AIR instructions
   data array.
 * Fix `elemPtrArray` not respecting const/mutable attribute of pointer
   in the result type.
 * Fix LLVM backend crashing when `updateDeclExports` is called before
   `updateDecl`/`updateFunc` (which is, according to the API, perfectly
   legal for the frontend to do).
 * Fix LLVM backend handling element pointer of pointer-to-array. It
   needed another index in the GEP otherwise LLVM saw the wrong type.
 * Fix LLVM test cases not returning 0 from main, causing test failures.
   Fixes a regression introduced in
   6a5094872f10acc629543cc7f10533b438d0283a.

 * Implement comptime shift-right.
 * Implement `@Type` for integers and `@TypeInfo` for integers.
 * Implement union initialization syntax.
 * Implement `zirFieldType` for unions.
 * Implement `elemPtrArray` for a runtime-known operand.

 * Make `zirLog2IntType` support RHS of shift being `comptime_int`. In
   this case it returns `comptime_int`.

The motivating test case for this commit was originally:

```zig
test "example" {
    var l: List(10) = undefined;
    l.array[1] = 1;
}

fn List(comptime L: usize) type {
    var T = u8;
    return struct {
        array: [L]T,
    };
}
```

However I changed it to:

```zig
test "example" {
    var l: List = undefined;
    l.array[1] = 1;
}

const List = blk: {
    const T = [10]u8;
    break :blk struct {
        array: T,
    };
};
```

Which ended up being a similar, smaller problem. The former test case
will require a similar solution in the implementation of comptime
function calls - checking if the result of the function call is a struct
or union, and using the child `Sema` before it is destroyed to resolve
the fields.
2021-08-20 15:41:57 -07:00
joachimschmidt557
f9e50a5830
stage2 ARM: implement bitshifting for 32-bit integers 2021-08-20 23:17:46 +02:00
Andrew Kelley
6a5094872f
Merge pull request #9587 from g-w1/sh
stage2: implement shr and shl
2021-08-19 23:47:44 -04:00
Jacob G-W
2e6ce11eb2 stage2: implement shr and boilerplate for shl
This implements it in the llvm and c backends.
x86_64 will have to be a little more work.
2021-08-19 16:18:40 -04:00
Jacob G-W
df10e998ee stage2 x86_64: enable bitwise and + or and add tests 2021-08-19 22:21:16 +03:00
Jakub Konka
da57d6df32 macho: simplify symbol management and resolution
instead of globally storing unresolved and tentative defs,
store indices to actual symbols in the functions that are responsible
for symbol resolution.
2021-08-12 10:20:57 +02:00
Andrew Kelley
799fedf612 stage2: pass some error union tests
* Value: rename `error_union` to `eu_payload` and clarify the intended
   usage in the doc comments. The way error unions is represented with
   Value is fixed to not have ambiguous values.
 * Fix codegen for error union constants in all the backends.
 * Implement the AIR instructions having to do with error unions in the
   LLVM backend.
2021-08-07 20:34:28 -07:00
Andrew Kelley
f81b2531cb stage2: pass some pointer tests
* New AIR instructions: ptr_add, ptr_sub, ptr_elem_val, ptr_ptr_elem_val
   - See the doc comments for details.
 * Sema: implement runtime pointer arithmetic.
 * Sema: implement elem_val for many-pointers.
 * Sema: support coercion from `*[N:s]T` to `[*]T`.
 * Type: isIndexable handles many-pointers.
2021-08-07 15:46:53 -07:00
Ryan Liptak
d31352ee85 Update all usages of mem.split/mem.tokenize for generic version 2021-08-06 02:01:47 -07:00
Andrew Kelley
ddf14323ea stage2: implement @truncate 2021-08-01 16:13:58 -07:00
joachimschmidt557
0d09c6aed8 stage2 ARM: fix stack alignment
Acording to the AAPCS32, the stack alignment at public interfaces
should be 8, not 4.
2021-08-01 03:57:08 -04:00
Andrew Kelley
1f95c50d9a codegen: cmp lowering treats bools the same as unsigned int
fixes a crash when lowering `a == b` and they are of type bool.
I'm not worried about floats; I think we will probably add separate AIR
instructions for floats.
2021-07-30 17:48:24 -07:00
joachimschmidt557
84039a57e4 stage2 codegen: Implement genTypedValue for enums 2021-07-30 17:53:33 -04:00
joachimschmidt557
f6b1fa9e29 stage2 codegen: genTypedValue for error unions and error sets 2021-07-30 13:22:33 -04:00
Andrew Kelley
040c6eaaa0 stage2: garbage collect unused anon decls
After this change, the frontend and backend cooperate to keep track of
which Decls are actually emitted into the machine code. When any backend
sees a `decl_ref` Value, it must mark the corresponding Decl `alive`
field to true.

This prevents unused comptime data from spilling into the output object
files. For example, if you do an `inline for` loop, previously, any
intermediate value calculations would have gone into the object file.
Now they are garbage collected immediately after the owner Decl has its
machine code generated.

In the frontend, when it is time to send a Decl to the linker, if it has
not been marked "alive" then it is deleted instead.

Additional improvements:
 * Resolve type ABI layouts after successful semantic analysis of a
   Decl. This is needed so that the backend has access to struct fields.
 * Sema: fix incorrect logic in resolveMaybeUndefVal. It should return
   "not comptime known" instead of a compile error for global variables.
 * `Value.pointerDeref` now returns `null` in the case that the pointer
   deref cannot happen at compile-time. This is true for global
   variables, for example. Another example is if a comptime known
   pointer has a hard coded address value.
 * Binary arithmetic sets the requireRuntimeBlock source location to the
   lhs_src or rhs_src as appropriate instead of on the operator node.
 * Fix LLVM codegen for slice_elem_val which had the wrong logic for
   when the operand was not a pointer.

As noted in the comment in the implementation of deleteUnusedDecl, a
future improvement will be to rework the frontend/linker interface to
remove the frontend's responsibility of calling allocateDeclIndexes.

I discovered some issues with the plan9 linker backend that are related
to this, and worked around them for now.
2021-07-29 19:30:37 -07:00
Andrew Kelley
a5c6e51f03 stage2: more principled approach to comptime references
* AIR no longer has a `variables` array. Instead of the `varptr`
   instruction, Sema emits a constant with a `decl_ref`.
 * AIR no longer has a `ref` instruction. There is no longer any
   instruction that takes a value and returns a pointer to it. If this
   is desired, Sema must either create an anynomous Decl and return a
   constant `decl_ref`, or in the case of a runtime value, emit an
   `alloc` instruction, `store` the value to it, and then return the
   `alloc`.
 * The `ref_val` Value Tag is eliminated. `decl_ref` should be used
   instead. Also added is `eu_payload_ptr` which points to the payload
   of an error union, given an error union pointer.

In general, Sema should avoid calling `analyzeRef` if it can be helped.
For example in the case of field_val and elem_val, there should never be
a reason to create a temporary (alloc or decl). Recent previous commits
made progress along that front.

There is a new abstraction in Sema, which looks like this:

    var anon_decl = try block.startAnonDecl();
    defer anon_decl.deinit();
    // here 'anon_decl.arena()` may be used
    const decl = try anon_decl.finish(ty, val);
    // decl is typically now used with `decl_ref`.

This pattern is used to upgrade `ref_val` usages to `decl_ref` usages.

Additional improvements:

 * Sema: fix source location resolution for calling convention
   expression.
 * Sema: properly report "unable to resolve comptime value" for loads of
   global variables. There is now a set of functions which can be
   called if the callee wants to obtain the Value even if the tag is
   `variable` (indicating comptime-known address but runtime-known value).
 * Sema: `coerce` resolves builtin types before checking equality.
 * Sema: fix `u1_type` missing from `addType`, making this type have a
   slightly more efficient representation in AIR.
 * LLVM backend: fix `genTypedValue` for tags `decl_ref` and `variable`
   to properly do an LLVMConstBitCast.
 * Remove unused parameter from `Value.toEnum`.

After this commit, some test cases are no longer passing. This is due to
the more principled approach to comptime references causing more
anonymous decls to get sent to the linker for codegen. However, in all
these cases the decls are not actually referenced by the runtime machine
code. A future commit in this branch will implement garbage collection
of decls so that unused decls do not get sent to the linker for codegen.
This will make the tests go back to passing.
2021-07-29 15:59:51 -07:00
Andrew Kelley
dc88864c97 stage2: implement @boolToInt
This is the first commit in which some behavior tests are passing for
both stage1 and stage2.
2021-07-27 17:08:37 -07:00
Andrew Kelley
31a59c229c stage2: improvements towards zig test
* Add AIR instruction: struct_field_val
   - This is part of an effort to eliminate the AIR instruction `ref`.
   - It's implemented for C backend and LLVM backend so far.
 * Rename `resolvePossiblyUndefinedValue` to `resolveMaybeUndefVal` just
   to save some columns on long lines.
 * Sema: add `fieldVal` alongside `fieldPtr` (renamed from
   `namedFieldPtr`). This is part of an effort to eliminate the AIR
   instruction `ref`. The idea is to avoid unnecessary loads, stores,
   stack usage, and IR instructions, by paying a DRY cost.

LLVM backend improvements:

 * internal linkage vs exported linkage is implemented, along with
   aliases. There is an issue with incremental updates due to missing
   LLVM API for deleting aliases; see the relevant comment in this commit.
   - `updateDeclExports` is hooked up to the LLVM backend now.
 * Fix usage of `Type.tag() == .noreturn` rather than calling `isNoReturn()`.
 * Properly mark global variables as mutable/constant.
 * Fix llvm type generation of function pointers
 * Fix codegen for calls of function pointers
 * Implement llvm type generation of error unions and error sets.
 * Implement AIR instructions: addwrap, subwrap, mul, mulwrap, div,
   bit_and, bool_and, bit_or, bool_or, xor, struct_field_ptr,
   struct_field_val, unwrap_errunion_err, add for floats, sub for
   floats.

After this commit, `zig test` on a file with `test "example" {}`
correctly generates and executes a test binary. However the
`test_functions` slice is undefined and just happens to be going into
the .bss section, causing the length to be 0. The next step towards
`zig test` will be replacing the `test_functions` Decl Value with the
set of test function pointers, before it is sent to linker/codegen.
2021-07-26 19:27:49 -07:00
Andrew Kelley
7b8cb881df stage2: improvements towards zig test
* There is now a main_pkg in addition to root_pkg. They are usually the
   same. When using `zig test`, main_pkg is the user's source file and
   root_pkg has the test runner.
 * scanDecl no longer looks for test decls outside the package being
   tested. honoring `--test-filter` is still TODO.
 * test runner main function has a void return value rather than
   `anyerror!void`
 * Sema is improved to generate better AIR for for loops on slices.
 * Sema: fix incorrect capacity calculation in zirBoolBr
 * Sema: add compile errors for trying to use slice fields as an lvalue.
 * Sema: fix type coercion for error unions
 * Sema: fix analyzeVarRef generating garbage AIR
 * C codegen: fix renderValue for error unions with 0 bit payload
 * C codegen: implement function pointer calls
 * CLI: fix usage text

 Adds 4 new AIR instructions:

  * slice_len, slice_ptr: to get the ptr and len fields of a slice.
  * slice_elem_val, ptr_slice_elem_val: to get the element value of
    a slice, and a pointer to a slice.

AstGen gains a new functionality:

 * One of the unused flags of struct decls is now used to indicate
   structs that are known to have non-zero size based on the AST alone.
2021-07-23 22:42:31 -07:00
Jakub Konka
def1359187 Merge remote-tracking branch 'origin/master' into zld-incremental-2 2021-07-22 09:34:44 +02:00
Jakub Konka
e05b1e0e07 macho: fix reloc generation for stubs and GOT entries
The current approach is somewhat hacky, however, works well for
one-off self-hosted linking.
2021-07-21 23:05:03 +02:00
Jakub Konka
845c906e6a macho: add relocations for GOT cells
in self-hosted compiler.
2021-07-21 17:58:05 +02:00
Andrew Kelley
bf09dd87b6 codegen: fix lowering of AIR br instruction
It incorrectly did not process the death of its operand.
2021-07-20 19:30:30 -07:00
Andrew Kelley
1097b0ec77 codegen: fix lowering of AIR return instruction
It incorrectly did not process the death of its operand. Additionally:

 * delete dead code accidentally introduced in fe14e339458a578657f3890f00d654a15c84422c
 * improve AIR printing code to include liveness data for operands.
   Now an exclamation point ("!") indicates the tombstone of an AIR
   instruction.
2021-07-20 18:51:40 -07:00
Lewis Gaul
bf8e347b1b Get codegen.zig to compile - use '{d}' format for Air.Inst.Index values 2021-07-20 12:19:16 -07:00
Andrew Kelley
4a0f38bb76 stage2: update LLVM backend to new AIR memory layout
Also fix compile errors when not using -Dskip-non-native
2021-07-20 12:19:16 -07:00
Andrew Kelley
d17f492017 stage2: miscellaneous fixes for the branch
* Breaking language change: inline assembly must use string literal
   syntax. This is in preparation for inline assembly improvements that
   involve more integration with the Zig language. This means we cannot
   rely on text substitution.
 * Liveness: properly handle inline assembly and function calls with
   more than 3 operands.
   - More than 35 operands is not yet supported. This is a low priority
     to implement.
   - This required implementation in codegen.zig as well.
 * Liveness: fix bug causing incorrect tomb bits.
 * Sema: enable switch expressions that are evaluated at compile-time.
   - Runtime switch instructions still need to be reworked in this
     branch. There was a TODO left here (by me) with a suggestion to do
     some bigger changes as part of the AIR memory reworking. Now that
     time has come and I plan to honor the suggestion in a future commit
     before merging this branch.
 * AIR printing: fix missing ')' on alive instructions.

We're back to "hello world" working for the x86_64 backend.
2021-07-20 12:19:16 -07:00
Andrew Kelley
8082660118 stage2: codegen.zig updated to new AIR memory layout 2021-07-20 12:19:16 -07:00
Jacob G-W
3a41e4430e codegen: add FnResult type which is a Result that removes externally_managed 2021-07-20 12:19:16 -07:00
Andrew Kelley
c09b973ec2 stage2: compile error fixes for AIR memory layout branch
Now the branch is compiling again, provided that one uses
`-Dskip-non-native`, but many code paths are disabled. The code paths
can now be re-enabled one at a time and updated to conform to the new
AIR memory layout.
2021-07-20 12:19:16 -07:00
Andrew Kelley
0f38f68696 stage2: Air and Liveness are passed ephemerally
to the link infrastructure, instead of being stored with Module.Fn. This
moves towards a strategy to make more efficient use of memory by not
storing Air or Liveness data in the Fn struct, but computing it on
demand, immediately sending it to the backend, and then immediately
freeing it.

Backends which want to defer codegen until flush() such as SPIR-V
must move the Air/Liveness data upon `updateFunc` being called and keep
track of that data in the backend implementation itself.
2021-07-20 12:19:16 -07:00
Andrew Kelley
913393fd3b stage2: first pass over Module.zig for AIR memory layout 2021-07-20 12:19:16 -07:00