12 Commits

Author	SHA1	Message	Date
David Rubin	05de6c279b	riscv: std.fmt.format running ... - implements `airSlice`, `airBitAnd`, `airBitOr`, `airShr`. - got a basic design going for the `airErrorName` but for some reason it simply returns empty bytes. will investigate further. - only generating `.got.zig` entries when not compiling an object or shared library - reduced the total amount of ops a mnemonic can have to 3, simplifying the logic	2024-06-13 02:20:47 -07:00
David Rubin	d9e0cafe64	riscv: add stage2_riscv to test matrix and bypass failing tests	2024-05-11 02:17:24 -07:00
Robin Voetter	075584a4d7	spirv: enable passing tests	2023-09-23 12:36:56 -07:00
Ali Chraghi	ccc490ef68	setup spirv backend in behavior tests	2023-05-11 20:31:52 +02:00
joachimschmidt557	d6e6162081	stage2 AArch64: unify callee-preserved regs on all targets ... also enables many passing behavior tests	2022-12-27 21:17:52 +08:00
Koakuma	f9e9ba784f	stage2: sparc64: Skip unimplemented tests	2022-12-10 21:51:46 +07:00
joachimschmidt557	b56b4428a3	stage2 ARM: fix recursive fibonacci ... Some handling of register_c_flag/register_v_flag was incorrect.	2022-05-22 21:02:32 +02:00
Jakub Konka	cfbc3537ef	x64: pass more behavior tests	2022-02-28 23:20:05 +01:00
Jakub Konka	25e4b16e25	Port more behavior tests	2022-02-22 21:57:42 +01:00
Andrew Kelley	c4df9bf56f	AstGen: fix while and for with unreachable bodies ... Companion commit to 61a53a587558ff1fe1b0ec98bb424022885edccf. This commit also moves over a bunch of behavior test cases to the passing-for-stage2 section.	2021-10-02 20:15:03 -07:00
Jacob G-W	9fffffb07b	fix code broken from previous commit	2021-06-21 17:03:03 -07:00
Andrew Kelley	4307436b99	move behavior tests from test/stage1/ to test/ ... And fix test cases to make them pass. This is in preparation for starting to pass behavior tests with self-hosted.	2021-04-29 15:54:04 -07:00