174 Commits

Author SHA1 Message Date
Andrew Kelley
389020009a AstGen: implement alignment on locals 2021-04-21 22:43:57 -07:00
Andrew Kelley
a62db38d90 AstGen: implement defer for break 2021-04-20 17:04:11 -07:00
Andrew Kelley
a59bcae59f AstGen: basic defer implementation 2021-04-20 17:04:11 -07:00
Andrew Kelley
e315120b79 AstGen: implement array initialization expressions 2021-04-19 23:23:24 -07:00
Andrew Kelley
2083208f19 AstGen: implement functions with inferred error sets
This commit also reclaims +2 ZIR instruction tags by moving the
following to `extended`:
 * func_var_args
 * func_extra
 * func_extra_var_args
The following ZIR instruction tag is added:
 * func_inferred
2021-04-19 15:03:41 -07:00
Andrew Kelley
ae495de54d AstGen: implement all the builtin functions 2021-04-18 22:38:41 -07:00
Andrew Kelley
e13fc6b119 stage2: make @import relative to the current file
previously, it was incorrectly relative to the package directory
2021-04-16 19:45:58 -07:00
Andrew Kelley
5ff45b3f44 stage2: use import list from ZIR to queue up more AstGen tasks 2021-04-16 17:28:28 -07:00
Andrew Kelley
01b4bf34ea stage2: AstGen improvements
* AstGen: represent compile errors in ZIR rather than returning
   `error.AnalysisFail`.
 * ZIR: remove decl_ref and decl_val instructions. These are replaced by
   `decl_ref_named` and `decl_val_named`, respectively, which will
   probably get renamed in the future to the instructions that were just
   deleted.
 * AstGen: implement `@This()`, `@fence()`, `@returnAddress()`, and
   `@src()`.
 * AstGen: struct_decl improved to support fields_len=0 but have decls.
 * AstGen: fix missing null bytes after compile error messages.
 * SrcLoc: no longer depend on `Decl`. Instead have an explicit field
   `parent_decl_node` which is an absolute AST Node index.
 * Module: `failed_files` table can have null value, in which case the
   key, which is a `*Scope.File`, will have ZIR errors in it.
 * ZIR: implement text rendering of struct decls.
 * CLI: introduce debug_usage and `zig astgen` command which is enabled
   when the compiler is built in debug mode.
2021-04-16 14:48:10 -07:00
Andrew Kelley
8387307807 AstGen: implement global variable decls 2021-04-15 20:34:21 -07:00
Andrew Kelley
3114115348 stage2: preliminary reworking for whole-file-AstGen
See #8516.

 * AstGen is now done on whole files at once rather than per Decl.

 * Introduce a new wait group for AstGen tasks. `performAllTheWork`
   waits for all AstGen tasks to be complete before doing Sema,
   single-threaded.
   - The C object compilation tasks are moved to be spawned after
     AstGen, since they only need to complete by the end of
     the function.

With this commit, the codebase compiles, but much more reworking is
needed to get things back into a useful state.
2021-04-15 19:06:39 -07:00
Andrew Kelley
9088d40e83 stage2: rename zir to Zir
since it now uses top level fields
2021-04-15 19:06:39 -07:00
Andrew Kelley
0170a242bb stage2: move zir.Code to become root level fields of zir.zig
next commit will do the rename
2021-04-15 19:06:39 -07:00
Andrew Kelley
df983b30d2 stage2: implement comptime division 2021-04-15 19:06:39 -07:00
Andrew Kelley
bcfebb4b2b stage2: improvements aimed at std lib integration
* AstGen: emit decl lookup ZIR instructions rather than directly
   looking up decls in AstGen. This is necessary because we want to
   reuse the same immutable ZIR code for multiple generic instantiations
   (and comptime function calls).
 * AstGen: fix using members_len instead of fields_len for struct decls.
 * structs: the struct_decl ZIR instruction is now also a block. This is
   so that the type expressions, default field value expressions, and
   alignment expressions can be evaluated in a scope that contains the
   decls from the struct namespace itself.
 * Add "std" and "builtin" packages to the builtin package.
 * Don't try to build glibc, musl, or mingw-w64 when using `-ofmt=c`.
 * builtin.zig is generated without `usingnamespace`.
 * builtin.zig takes advantage of `std.zig.fmtId` for CPU features.
 * A first pass at implementing `usingnamespace`. It's problematic and
   should either be deleted, or polished, before merging this branch.
 * Sema: allow explicitly specifying the namespace in which to look up
   Decls. This is used by `struct_decl` in order to put the decls from
   the struct namespace itself in scope when evaluating the type
   expressions, default value expressions, and alignment expressions.
 * Module: fix `analyzeNamespace` assuming that it is the top-level root
   declaration node.
 * Sema: implement comptime and runtime cmp operator.
 * Sema: implement peer type resolution for enums and enum literals.
 * Pull in the changes from master branch:
   262e09c482d98a78531c049a18b7f24146fe157f.
 * ZIR: complete out simple_ptr_type debug printing
2021-04-15 19:06:39 -07:00
Andrew Kelley
a4bb7c8bb1 stage2: remove redundant source hash 2021-04-15 19:06:39 -07:00
Andrew Kelley
f458192e56 stage2: entry point via std lib and proper updated file detection
Instead of Module setting up the root_scope with the root source file,
instead, Module relies on the package table graph being set up properly,
and inside `update()`, it does the equivalent of `_ = @import("std");`.
This, in term, imports start.zig, which has the logic to call main (or
not). `Module` no longer has `root_scope` - the root source file is no
longer special, it's just in the package table mapped to "root".

I also went ahead and implemented proper detection of updated files.
mtime, inode, size, and source hash are kept in `Scope.File`.
During an update, iterate over `import_table` and stat each file to find
out which ones are updated.

The source hash is redundant with the source hash used by the struct
decl that corresponds to the file, so it should be removed in a future
commit before merging the branch.

 * AstGen: add "previously declared here" notes for variables shadowing
   decls.
 * Parse imports as structs. Module now calls `AstGen.structDeclInner`,
   which is called by `AstGen.containerDecl`.
   - `importFile` is a bit kludgy with how it handles the top level Decl
     that kinda gets merged into the struct decl at the end of the
     function. Be on the look out for bugs related to that as well as
     possibly cleaner ways to implement this.
 * Module: factor out lookupDeclName into lookupIdentifier and lookupNa
 * Rename `Scope.Container` to `Scope.Namespace`.
 * Delete some dead code.

This branch won't work until `usingnamespace` is implemented because it
relies on `@import("builtin").OutputMode` and `OutputMode` comes from a
`usingnamespace`.
2021-04-15 19:06:39 -07:00
jacob gw
0d92bd474f stage2: fix case where public variables did not work 2021-04-09 11:54:38 -07:00
Andrew Kelley
f75cdd1acd
Merge pull request #8470 from ziglang/stage2-start
stage2: blaze the trail for std lib integration
2021-04-09 10:15:46 -07:00
jacob gw
afe5862111 stage2: add error for private decls accessed from other files 2021-04-09 10:05:15 -07:00
Andrew Kelley
1b702f8ddb stage2: fix the memory leaks 2021-04-08 20:52:02 -07:00
Andrew Kelley
61b868f9a5 stage2: simplify Decl src_node field
Also fix "previous definition here" error notes to be correct.
2021-04-08 20:37:19 -07:00
Andrew Kelley
482b995a49 stage2: blaze the trail for std lib integration
This branch adds "builtin" and "std" to the import table when using the
self-hosted backend.

"builtin" gains one additional item:

```
pub const zig_is_stage2 = true; // false when using stage1 backend
```

This allows the std lib to do conditional compilation based on detecting
which backend is being used. This will be removed from builtin as soon
as self-hosted catches up to feature parity with stage1.
Keep a sharp eye out - people are going to be tempted to abuse this.
The general rule of thumb is do not use `builtin.zig_is_stage2`. However
this commit breaks the rule so that we can gain limited start.zig support
as we incrementally improve the self-hosted compiler.

This commit also implements `fullyQualifiedNameHash` and related
functionality, which effectively puts all Decls in their proper
namespaces. `fullyQualifiedName` is not yet implemented.

Stop printing "todo" log messages for test decls unless we are in test
mode.

Add "previous definition here" error notes for Decl name collisions.

This commit does not bring us yet to a newly passing test case.

Here's what I'm working towards:

```zig
const std = @import("std");

export fn main() c_int {
    const a = std.fs.base64_alphabet[0];
    return a - 'A';
}
```

Current output:

```
$ ./zig-cache/bin/zig build-exe test.zig
test.zig:3:1: error: TODO implement more analyze elemptr
zig-cache/lib/zig/std/start.zig:38:46: error: TODO implement structInitExpr ty
```

So the next steps are clear:
 * Sema: improve elemptr
 * AstGen: implement structInitExpr
2021-04-08 19:05:05 -07:00
Luuk de Gram
ff5774d93d
Refactor link/wasm.zig to use offset table
This refactor inserts an offset table into wasm's data section
where each offset points to the actual data region.
This means we can keep offset indexes consistant and do not
have to perform any computer to determine where in the data section
something like a static string exists. Instead during runtime
it will load the data offset onto the stack.
2021-04-08 22:47:08 +02:00
Luuk de Gram
1bd5552fc1
Calculate data length to ensure correct pointer offsets 2021-04-08 22:47:08 +02:00
Andrew Kelley
b9e508c410 stage2: revert to only has_decl and export ZIR support
Reverting most of the code from the previous commits in this branch.
Will pull in the code with modifications bit by bit.
2021-04-08 11:29:31 -07:00
Timon Kruiper
a483e38df6 stage2: fix bug where invalid ZIR was generated
The following code caused an assertion to be hit:
```
pub fn main() void {
    var e: anyerror!c_int = error.Foo;
    const i = e catch 69;
    assert(69 - i == 0);
}
```
2021-04-08 14:23:18 +02:00
Timon Kruiper
ac14b52e85 stage2: add support for start.zig
This adds a simplified start2.zig that the current stage2 compiler is
able to generate code for.
2021-04-08 14:23:18 +02:00
Timon Kruiper
272fe0cbfe stage2: fix bug in ZIR gen of global comptime block
A global comptime block did not end with a break_inline instruction
which caused an assertion to be hit.
2021-04-08 14:20:40 +02:00
Andrew Kelley
e730172e47 stage2: fix switch validation of handling all enum values
There were several problems, all fixed:
 * AstGen was storing field names as references to the original
   source code bytes. However, that data would be destroyed when the
   source file is updated. Now, it correctly stores the field names in
   the Decl arena for the enum. The same fix applies to error set field
   names.
 * Sema was missing a memset inside `analyzeSwitch`, leaving the "seen
   enum fields" array with undefined memory. Now that they are all
   properly set to null, the validation works.
 * Moved the "enum declared here" note to the end. It looked weird
   interrupting the notes for which enum values were missing.
2021-04-07 22:02:45 -07:00
Andrew Kelley
12087d4cba stage2: fix incremental compilation handling of parse errors
Before, incremental compilation would crash when trying to emit compile
errors for the update after introducing a parse error.

Parse errors are handled by not invalidating any existing semantic
analysis. However, only the parse error must be reported, with all the
other errors suppressed. Once the parse error is fixed, the new file can
be treated as an update to the previously-succeeded update.
2021-04-07 20:36:01 -07:00
Andrew Kelley
4996c2b6a9 stage2: fix incremental compilation Decl deletion logic
* `analyzeContainer` now has an `outdated_decls` set as well as
   `deleted_decls`. Instead of queuing up outdated Decls for re-analysis
   right away, they are added to this new set. When processing the
   `deleted_decls` set, we remove deleted Decls from the
   `outdated_decls` set, to avoid deleted Decl pointers from being in
   the work_queue. Only after processing the deleted decls do we add
   analyze_decl work items to the queue.

 * Module.deletion_set is now an `AutoArrayHashMap` rather than `ArrayList`.
   `declareDeclDependency` will now remove a Decl from it as appropriate.
   When processing the `deletion_set` in `Compilation.performAllTheWork`,
   it now assumes all Decl in the set are to be deleted.

 * Fix crash when handling parse errors. Currently we unload the
   `ast.Tree` if any parse errors occur. Previously the code emitted a
   LazySrcLoc pointing to a token index, but then when we try to resolve
   the token index to a byte offset to create a compile error message,
   the  ast.Tree` would be unloaded. Now we use
   `LazySrcLoc.byte_abs` instead of `token_abs` so the error message can
   be created even with the `ast.Tree` unloaded.

Together, these changes solve a crash that happened with incremental
compilation when Decls were added and removed in some combinations.
2021-04-07 19:54:28 -07:00
Andrew Kelley
4e8fb9e6a5 Sema: DRY up enum field analysis and add "declared here" notes 2021-04-07 11:26:07 -07:00
Andrew Kelley
b40d36c90b stage2: implement simple enums
A simple enum is an enum which has an automatic integer tag type,
all tag values automatically assigned, and no top level declarations.
Such enums are created directly in AstGen and shared by all the
generic/comptime instantiations of the surrounding ZIR code. This
commit implements, but does not yet add any test cases for, simple enums.

A full enum is an enum for which any of the above conditions are not
true. Full enums are created in Sema, and therefore will create a unique
type per generic/comptime instantiation. This commit does not implement
full enums. However the `enum_decl_nonexhaustive` ZIR instruction is
added and the respective Type functions are filled out.

This commit makes an improvement to ZIR code, removing the decls array
and removing the decl_map from AstGen. Instead, decl_ref and
decl_val ZIR instructions index into the `owner_decl.dependencies`
ArrayHashMap. We already need this dependencies array for incremental
compilation purposes, and so repurposing it to also use it for ZIR decl
indexes makes for efficient memory usage.

Similarly, this commit fixes up incorrect memory management by removing
the `const` ZIR instruction. The two places it was used stored memory in
the AstGen arena, which may get freed after Sema. Now it properly sets
up a new anonymous Decl for error sets and uses a normal decl_val
instruction.

The other usage of `const` ZIR instruction was float literals. These are
now changed to use `float` ZIR instruction when the value fits inside
`zir.Inst.Data` and `float128` otherwise.

AstGen + Sema: implement int_to_enum and enum_to_int. No tests yet; I expect to
have to make some fixes before they will pass tests. Will do that in the
branch before merging.

AstGen: fix struct astgen incorrectly counting decls as fields.

Type/Value: give up on trying to exhaustively list every tag all the
time. This makes the file more manageable. Also found a bug with
i128/u128 this way, since the name of the function was more obvious when
looking at the tag values.

Type: implement abiAlignment and abiSize for structs. This will need to
get more sophisticated at some point, but for now it is progress.

Value: add new `enum_field_index` tag.
Value: add hash_u32, needed when using ArrayHashMap.
2021-04-06 18:17:37 -07:00
Andrew Kelley
d47f0abd5b stage2: Sema: implement validate_struct_init_ptr 2021-04-02 21:06:09 -07:00
Andrew Kelley
97d7fddfb7 stage2: progress towards basic structs
Introduce `ResultLoc.none_or_ref` which is used by field access
expressions to avoid unnecessary loads when the field access itself
will do the load. This turns:

```zig
p.y - p.x - p.x
```

from

```zir
  %14 = load(%4) node_offset:8:12
  %15 = field_val(%14, "y") node_offset:8:13
  %16 = load(%4) node_offset:8:18
  %17 = field_val(%16, "x") node_offset:8:19
  %18 = sub(%15, %17) node_offset:8:16
  %19 = load(%4) node_offset:8:24
  %20 = field_val(%19, "x") node_offset:8:25
```

to

```zir
  %14 = field_val(%4, "y") node_offset:8:13
  %15 = field_val(%4, "x") node_offset:8:19
  %16 = sub(%14, %15) node_offset:8:16
  %17 = field_val(%4, "x") node_offset:8:25
```

Much more compact. This requires `Sema.zirFieldVal` to support both
pointers and non-pointers.

C backend: Implement typedefs for struct types, as well as the following
TZIR instructions:
 * mul
 * mulwrap
 * addwrap
 * subwrap
 * ref
 * struct_field_ptr

Note that add, addwrap, sub, subwrap, mul, mulwrap instructions are all
incorrect currently and need to be updated to properly handle wrapping
and non wrapping for signed and unsigned.

C backend: change indentation delta to 1, to make the output smaller and
to process fewer bytes.

I promise I will add a test case as soon as I fix those warnings that
are being printed for my test case.
2021-04-02 19:11:51 -07:00
Andrew Kelley
8ebfdc14f6 stage2: implement structs in the frontend
New ZIR instructions:
 * struct_decl_packed
 * struct_decl_extern

New TZIR instruction: struct_field_ptr

Introduce `Module.Struct`. It uses `Value` to store default values and
abi alignments.

Implemented Sema.analyzeStructFieldPtr and zirStructDecl.

Some stuff I changed from `@panic("TODO")` to `log.warn("TODO")`.
It's becoming more clear that we need the lazy value mechanism soon;
Type is becoming unruly, and some of these functions have too much logic
given that they don't have any context for memory management or error
reporting.
2021-04-01 22:39:09 -07:00
Andrew Kelley
50bcfb8c90 stage2: implement struct init syntax with ptr result loc 2021-04-01 11:58:55 -07:00
Andrew Kelley
c9e31febf8 stage2: finish implementation of LazySrcLoc 2021-03-31 23:00:00 -07:00
Andrew Kelley
b27d052676 stage2: finish source location reworkings in the branch
* remove the LazySrcLoc.todo tag
 * finish updating Sema and AstGen, remove the last of the
   `@panic("TODO")`.
2021-03-31 21:36:32 -07:00
Andrew Kelley
3cebaaad1c astgen: improved handling of coercion
GenZir struct now has rl_ty_inst field which tracks the result location
type (if any) a block expects all of its results to be coerced to.

Remove a redundant coercion on const local initialization with a
specified type.

Switch expressions, during elision of store_to_block_ptr instructions,
now re-purpose them to be type coercion when the block has a type in the
result location.
2021-03-31 18:05:37 -07:00
Andrew Kelley
195ddab2be Sema: implement switch expressions
The logic for putting ranges into the else prong is moved from AstGen to
Sema. However, logic to emit multi-items the same as single-items cannot
be done until TZIR supports mapping multiple items to the same block of
code. This will be simple to represent when we do the upcoming TZIR memory
layout changes.

Not yet implemented in this commit is the validation of duplicate
values. The trick is going to be emitting error messages with accurate
source locations, without adding extra source nodes to the ZIR
switch instruction.

This will be done by computing the respective AST node based on the
switch node (which we do have available), only when a compile error
occurs and we need to know the source location to attach the message to.
2021-03-29 21:59:08 -07:00
Andrew Kelley
623d5f442c stage2: guidance on how to implement switch expressions
Here's what I think the ZIR should be. AstGen is not yet implemented to
match this, and the main implementation of analyzeSwitch in Sema is not
yet implemented to match it either.

Here are some example byte size reductions from master branch, with the
ZIR memory layout from this commit:

```
switch (foo) {
  a => 1,
  b => 2,
  c => 3,
  d => 4,
}
```

184 bytes (master) => 40 bytes (this branch)

```
switch (foo) {
  a, b => 1,
  c..d, e, f => 2,
  g => 3,
  else => 4,
}
```

240 bytes (master) => 80 bytes (this branch)
2021-03-28 23:12:26 -07:00
Andrew Kelley
8f469c1127 stage2: fix error sets 2021-03-28 19:40:21 -07:00
jacob gw
0005b34637 stage2: implement sema for @errorToInt and @intToError 2021-03-28 18:22:01 -07:00
Isaac Freund
f80f8a7a78
AstGen: pass *GenZir as the first arg, not *Module
This avoids the unnecessary scope.getGenZir() virtual call for both
convenience and performance.
2021-03-28 22:42:17 +02:00
Isaac Freund
d123a5ec67
AstGen: scope result location related functions 2021-03-28 19:53:38 +02:00
Isaac Freund
402f87a213
stage2: rename WipZirCode => AstGen, astgen.zig => AstGen.zig 2021-03-28 19:10:10 +02:00
Andrew Kelley
1f5617ac07 stage2: implement bitwise expr and error literals 2021-03-26 23:46:37 -07:00
Andrew Kelley
da731e18c9 stage2: implement source location: .node_offset_var_decl_ty 2021-03-26 18:35:15 -07:00