378 Commits

Author SHA1 Message Date
joachimschmidt557
9892684d35 stage2 ARM: spill insts currently in compare flags if necessary 2021-12-18 15:23:25 -08:00
Jakub Konka
4b5f8bca5e stage2: clean up tests
* move darwin tests into respective architecture test files: `x86_64`
and `aarch64`
* run majority of `x86_64` tests on macOS
2021-12-15 17:28:48 +01:00
joachimschmidt557
2f18c5955a stage2 ARM: Implement calling with stack parameters 2021-12-04 18:16:23 -08:00
Luuk de Gram
adf059f272
wasm: Update wasm stage2 test backend to use 'main' 2021-11-29 08:05:51 +01:00
Luuk de Gram
deb8d0765b
wasm: Fix text cases and add pointer test cases
Ensure all previous test cases are still passing, as well as add some basic tests for now
for testing pointers to the stack.

This means we can start implementing wasm's C ABI found at: https://github.com/WebAssembly/tool-conventions/blob/main/BasicCABI.md

We also simplified the block logic by always using 'void' block types and instead writing the value to a local,
which can then be referenced by continues instructions, as done currently by AIR.
Besides this, we also no longer need to insert blocks at an offset, as we simply write the saved temporary
after we create the block.
2021-11-21 21:07:55 +01:00
joachimschmidt557
e8112f7744 stage2 RISCV64: implement basic function prologue and epilogue 2021-11-20 19:25:59 +01:00
Jakub Konka
19e5663869
Merge pull request #9935 from g-w1/plan9-std
add plan9 support to std
2021-11-11 10:45:00 -08:00
joachimschmidt557
4168b01e7a
stage2 AArch64: implement airCondBr 2021-11-10 20:05:35 +01:00
Jakub Konka
91c3206b45 macho: use start.zig for macOS entrypoint
This effectively allows us to compile

```zig
pub fn main() void {}
```

which then calls into `std.start`.

Changes required to make this happen:
* handle signed int to immediate in x86_64 and aarch64 codegen
* ensure that on arm64 macOS, `.x19` is a caller-preserved register -
  I'm not sure about that one at all and would like to brainstorm it
  with anyone interested and especially Joachim.
* finally, fix a bug in the linker - mark new got entry as dirty upon
  atom growth.
2021-11-10 11:33:24 -05:00
Jacob G-W
bfb88b2d0d plan9: add test for std 2021-11-09 07:08:27 -05:00
Andrew Kelley
dfb3231959 stage2: implement switching on unions
* AstGen: Move `refToIndex` and `indexToRef` to Zir
 * ZIR: the switch_block_*_* instruction tags are collapsed into one
   switch_block tag which uses 4 bits for flags, and reduces the
   scalar_cases_len field from 32 to 28 bits.
   This freed up more ZIR tags, 2 of which are now used for
   `switch_cond` and `switch_cond_ref` for producing the switch
   condition value. For example, for union values it returns the
   corresponding enum value.
 * switching with multiple cases and ranges is not yet supported because
   I want to change the ZIR encoding to store index pointers into the
   extra array rather than storing prong indexes. This will avoid O(N^2)
   iteration over prongs.
 * AstGen now adds a `switch_cond` on the operand and then passes the
   result of that to the `switch_block` instruction.
 * Sema: partially implement `switch_capture_*` instructions.
 * Sema: `unionToTag` notices if the enum type has only one possible value.
2021-10-19 20:22:47 -07:00
Matthew Borkowski
135cb529de astgen.zig: fix emitting wrong error unwrapping instructions in tryExpr 2021-10-19 13:44:48 -04:00
Matthew Borkowski
ea45062d82 stage2: add astgen errors for untyped union fields and union field values without inferred tag type 2021-10-09 20:39:50 -04:00
Josh Soref
664941bf14
Spelling corrections (#9833)
Signed-off-by: Josh Soref <jsoref@users.noreply.github.com>
Co-authored-by: Josh Soref <jsoref@users.noreply.github.com>
2021-09-24 13:39:20 -04:00
Martin Wickham
d86678778a Fix failing tests and windows link dependencies 2021-09-22 14:39:02 -05:00
Robin Voetter
5a142dfa56 Address Spaces: LLVM F segment address space test 2021-09-20 02:29:04 +02:00
Robin Voetter
90a945b38c Address Spaces: Split out stage2 address llvm tests to individual cases
This previously caused a test case to crash due to lingering llvm state.
2021-09-20 02:29:04 +02:00
Robin Voetter
e09465fc49 Address Spaces: Chaining tests 2021-09-20 02:29:04 +02:00
Robin Voetter
2f43749c2b Address Spaces: Move stage 2 tests to stage2/llvm.zig 2021-09-20 02:29:04 +02:00
Andrew Kelley
dbe9a5114e stage2: implement @setAlignStack and 128-bit cmpxchg
* test runner is improved to respect `error.SkipZigTest`
 * start code is improved to `@setAlignStack(16)` before calling main()
 * the newly passing behavior test has a workaround for the fact that
   stage2 cannot yet call `std.Target.x86.featureSetHas()` at comptime.
   This is blocking on comptime closures. The workaround is that there
   is a new decl `@import("builtin").stage2_x86_cx16` which is a `bool`.
 * Implement `@setAlignStack`. This language feature should be re-evaluated
   at some point - I'll file an issue for it.
 * LLVM backend: apply/remove the cold attribute and noinline attribute
   where appropriate.
 * LLVM backend: loads and stores are properly annotated with alignment
   and volatile attributes.
 * LLVM backend: allocas are properly annotated with alignment.
 * Type: fix integers reporting wrong alignment for 256-bit integers and
   beyond. Once you get to 16 byte aligned, there is no further
   alignment for larger integers.
2021-09-16 21:03:55 -07:00
Jakub Konka
a38b636045 Merge remote-tracking branch 'origin/master' into zld-incr 2021-09-13 23:40:38 +02:00
Jakub Konka
760241ce50 macho: use the cache system to know if need to relink objects
This applies to stage2 where we make use of the cache system to work
out if we need to relink objects when performing incremental updates.
When the process is restarted however, while in principle the idea is
to carry on where we left off by reparsing the prelinked binary from
file, the required machinery is not there yet, and therefore we always
fully relink upon restart.
2021-09-13 23:02:21 +02:00
Meghan Denny
cf9684ce75 stage2: add @rem tests to llvm and c backends 2021-08-30 19:48:31 -07:00
Andrew Kelley
f1f28af188 fix stage2 test cases expecting wrong line numbers
Previous commit shifted everything down in the start.zig file, and
unfortunately our stage2 test harness depends on absolute line
numbers for a couple tests.
2021-08-24 13:42:31 -07:00
Jacob G-W
4ac37eb484 stage2 Air: add struct_field_ptr_index_{0..3}
Since these are very common, it will save memory.
2021-08-21 23:52:55 -04:00
joachimschmidt557
5806c386eb stage2 codegen: re-allocate result register in finishAir
In some cases (such as bitcast), an operand may be the same MCValue as
the result. If that operand died and was a register, it was freed by
processDeath. We have to "re-allocate" the register.
2021-08-20 19:06:30 -04:00
Andrew Kelley
a2438357e1
Merge pull request #9597 from joachimschmidt557/stage2-arm-bitshift
stage2 ARM: implement bitshifts
2021-08-20 19:05:05 -04:00
Andrew Kelley
0cd361219c stage2: field type expressions support referencing locals
The big change in this commit is making `semaDecl` resolve the fields if
the Decl ends up being a struct or union. It needs to do this while
the `Sema` is still in scope, because it will have the resolved AIR
instructions that the field type expressions possibly reference. We do
this after the decl is populated and set to `complete` so that a `Decl`
may reference itself.

Everything else is fixes and improvements to make the test suite pass
again after making this change.

 * New AIR instruction: `ptr_elem_ptr`
   - Implemented for LLVM backend
 * New Type tag: `type_info` which represents `std.builtin.TypeInfo`. It
   is used by AstGen for the operand type of `@Type`.
 * ZIR instruction `set_float_mode` uses `coerced_ty` to avoid
   superfluous `as` instruction on operand.
 * ZIR instruction `Type` uses `coerced_ty` to properly handle result
   location type of operand.

 * Fix two instances of `enum_nonexhaustive` Value Tag not handled
   properly - it should generally be handled the same as `enum_full`.
 * Fix struct and union field resolution not copying Type and Value
   objects into its Decl arena.
 * Fix enum tag value resolution discarding the ZIR=>AIR instruction map
   for the child Sema, when they still needed to be accessed.
 * Fix `zirResolveInferredAlloc` use-after-free in the AIR instructions
   data array.
 * Fix `elemPtrArray` not respecting const/mutable attribute of pointer
   in the result type.
 * Fix LLVM backend crashing when `updateDeclExports` is called before
   `updateDecl`/`updateFunc` (which is, according to the API, perfectly
   legal for the frontend to do).
 * Fix LLVM backend handling element pointer of pointer-to-array. It
   needed another index in the GEP otherwise LLVM saw the wrong type.
 * Fix LLVM test cases not returning 0 from main, causing test failures.
   Fixes a regression introduced in
   6a5094872f10acc629543cc7f10533b438d0283a.

 * Implement comptime shift-right.
 * Implement `@Type` for integers and `@TypeInfo` for integers.
 * Implement union initialization syntax.
 * Implement `zirFieldType` for unions.
 * Implement `elemPtrArray` for a runtime-known operand.

 * Make `zirLog2IntType` support RHS of shift being `comptime_int`. In
   this case it returns `comptime_int`.

The motivating test case for this commit was originally:

```zig
test "example" {
    var l: List(10) = undefined;
    l.array[1] = 1;
}

fn List(comptime L: usize) type {
    var T = u8;
    return struct {
        array: [L]T,
    };
}
```

However I changed it to:

```zig
test "example" {
    var l: List = undefined;
    l.array[1] = 1;
}

const List = blk: {
    const T = [10]u8;
    break :blk struct {
        array: T,
    };
};
```

Which ended up being a similar, smaller problem. The former test case
will require a similar solution in the implementation of comptime
function calls - checking if the result of the function call is a struct
or union, and using the child `Sema` before it is destroyed to resolve
the fields.
2021-08-20 15:41:57 -07:00
joachimschmidt557
224fe49be2
stage2 ARM: add test cases for bit shifts 2021-08-20 23:37:41 +02:00
Jacob G-W
2e22f7e5a5 stage2: implement shl
This is implemented in the llvm and cbe backends.
x86_64 will take a bit more time.
2021-08-19 16:18:42 -04:00
Jacob G-W
2e6ce11eb2 stage2: implement shr and boilerplate for shl
This implements it in the llvm and c backends.
x86_64 will have to be a little more work.
2021-08-19 16:18:40 -04:00
Takeshi Yoneda
97560cd915 Merge remote-tracking branch 'origin' into libc-wasi-test 2021-08-09 14:39:26 +09:00
Andrew Kelley
7d0de54ad4 stage2: fix return pointer result locations
* Introduce `ret_load` ZIR instruction which does return semantics
   based on a corresponding `ret_ptr` instruction. If the return type of
   the function has storage for the return type, it simply returns.
   However if the return type of the function is by-value, it loads the
   return value from the `ret_ptr` allocation and returns that.

 * AstGen: improve `finishThenElseBlock` to not emit break instructions
   after a return instruction in the same block.

 * Sema: `ret_ptr` instruction works correctly in comptime contexts.
   Same with `alloc_mut`.

The test case with a recursive inline function having an implicitly
comptime return value now has a runtime return value because of the fact
that it calls a function in a non-comptime context.
2021-08-06 19:53:04 -07:00
Luuk de Gram
6e139d124b
wasm: Resolve feedback (wrapping arbitrary int sizes)
- This ensures we honor the user's integer size when performing wrapping operations.
- Also, instead of using ensureCapacity, we now use ensureUnusedCapacity.
2021-08-01 21:30:06 +02:00
Luuk de Gram
a861b7d160
wasm: Test cases for optionals 2021-08-01 11:07:23 +02:00
Luuk de Gram
e58976542b
wasm: Test cases for wrap+intcast instructions 2021-08-01 11:07:23 +02:00
joachimschmidt557
84039a57e4 stage2 codegen: Implement genTypedValue for enums 2021-07-30 17:53:33 -04:00
Andrew Kelley
040c6eaaa0 stage2: garbage collect unused anon decls
After this change, the frontend and backend cooperate to keep track of
which Decls are actually emitted into the machine code. When any backend
sees a `decl_ref` Value, it must mark the corresponding Decl `alive`
field to true.

This prevents unused comptime data from spilling into the output object
files. For example, if you do an `inline for` loop, previously, any
intermediate value calculations would have gone into the object file.
Now they are garbage collected immediately after the owner Decl has its
machine code generated.

In the frontend, when it is time to send a Decl to the linker, if it has
not been marked "alive" then it is deleted instead.

Additional improvements:
 * Resolve type ABI layouts after successful semantic analysis of a
   Decl. This is needed so that the backend has access to struct fields.
 * Sema: fix incorrect logic in resolveMaybeUndefVal. It should return
   "not comptime known" instead of a compile error for global variables.
 * `Value.pointerDeref` now returns `null` in the case that the pointer
   deref cannot happen at compile-time. This is true for global
   variables, for example. Another example is if a comptime known
   pointer has a hard coded address value.
 * Binary arithmetic sets the requireRuntimeBlock source location to the
   lhs_src or rhs_src as appropriate instead of on the operator node.
 * Fix LLVM codegen for slice_elem_val which had the wrong logic for
   when the operand was not a pointer.

As noted in the comment in the implementation of deleteUnusedDecl, a
future improvement will be to rework the frontend/linker interface to
remove the frontend's responsibility of calling allocateDeclIndexes.

I discovered some issues with the plan9 linker backend that are related
to this, and worked around them for now.
2021-07-29 19:30:37 -07:00
Takeshi Yoneda
1e20a62126 WASI,libc: enable tests.
Signed-off-by: Takeshi Yoneda <takeshi@tetrate.io>
2021-07-27 09:01:00 +09:00
Luuk de Gram
30376a82b2
Re-enable switch test cases and fix regressions 2021-07-24 20:05:41 +02:00
Andrew Kelley
885477e2df stage2: disable wasm switch test case for now
The wasm codegen for switch was using br_if opcodes, but it needs to be
reworked to use a br_table opcode instead.
2021-07-20 19:01:19 -07:00
Jacob G-W
968d1ecf17 stage2 plan9: add aarch64 support 2021-07-11 01:58:26 -04:00
Jacob G-W
7b5d139fd3 plan9 codegen, add tests
They generate an object file, but do not execute yet,
since we don't have something to execute them with.
2021-07-09 14:20:36 -04:00
g-w1
1f0b77b3b8
stage2 type.zig: implement eql of error unions (#9334) 2021-07-08 14:35:43 -04:00
Andrew Kelley
9dbe684854 C backend: cleanups to wrapping int operations
* less branching by passing parameters in the main op code switch.
 * properly pass the target when asking the type system for int info.
 * handle u8, i16, etc when it is represented using
   int_unsigned/int_signed tag.
 * compile error instead of assertion failure for unimplemented cases
   (greater than 64 bits integer).
 * control flow cleanups
 * zig.h: expand macros into inline functions
 * reduce the complexity of the test case by making it one test case
   that calls multiple functions. Also fix the problem of c_int max
   value mismatch between host and target.
2021-07-08 11:21:06 -07:00
Matt Knight
fb16633ecb C backend: add/sub/mul wrapping for the C backend 2021-07-08 09:56:40 -07:00
Andrew Kelley
c2e66d9bab stage2: basic inferred error set support
* Inferred error sets are stored in the return Type of the function,
   owned by the Module.Fn. So it cleans up that memory in deinit().
 * Sema: update the inferred error set in zirRetErrValue
   - Update relevant code in wrapErrorUnion
 * C backend: improve some some instructions to take advantage of
   liveness analysis to avoid being emitted when unused.
 * C backend: when an error union has a payload type with no runtime
   bits, emit the error union as the same type as the error set.
2021-07-07 20:47:21 -07:00
Andrew Kelley
5816997ae7 stage2: get tests passing
* implement enough of ret_err_value to pass wasm tests
 * only do the proper `@panic` implementation for the backends which
   support it, which is currently only the C backend. The other backends
   will see `@breakpoint(); unreachable;` same as before.
   - I plan to do AIR memory layout reworking as a prerequisite to
     fixing other backends, because that will help me put all the
     constants up front, which will allow the codegen to lower to memory
     without jumps.
 * `@panic` is implemented using anon decls for the message. Makes it
   easier on the backends. Might want to look into re-using decls for
   this in the future.
 * implement DWARF .debug_info for pointer-like optionals.
2021-07-07 14:17:04 -07:00
Andrew Kelley
13f04e3012 stage2: implement @panic and beginnigs of inferred error sets
* ZIR: add two instructions:
   - ret_err_value_code
   - ret_err_value
 * AstGen: add countDefers and utilize it to emit more efficient ZIR for
   return expressions in the presence of defers.
 * AstGen: implement |err| payloads for `errdefer` syntax.
   - There is not an "unused capture" error for it yet.
 * AstGen: `return error.Foo` syntax gets a hot path in return
   expressions, using the new ZIR instructions. This also is part of
   implementing inferred error sets, since we need to tell Sema to add
   an error value to the inferred error set before it gets coerced.
 * Sema: implement `@setCold`.
   - Implement `@setCold` support for C backend.
 * `@panic` and regular safety panics such as `unreachable` now properly
   invoke `std.builtin.panic`.
 * C backend: improve pointer and function value rendering.
 * C linker: fix redundant typedefs.
 * Add Type.error_set_inferred.
 * Fix Value.format for enum_literal, enum_field_index, bytes.
 * Remove the C backend test that checks for identical text

I measured a 14% reduction in Total ZIR Bytes from master branch
for std/os.zig.
2021-07-07 00:39:23 -07:00
Andrew Kelley
c5c23db627 tokenizer: clean up invalid token error
It now displays the byte with proper printability handling. This makes
the relevant compile error test case no longer a regression in quality
from stage1 to stage2.
2021-07-02 13:28:31 -07:00